vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)

Question

I am trying to create a simple memory that stores vectors whenever the clock is 1 and wrenable is 1 (and likewise for reading), but unfortunately I've been facing timing issues:

(我正在尝试创建一个简单的存储器，该存储器在时钟为1且wrenable为1时存储矢量（同样用于读取），但是不幸的是，我一直面临着计时问题：)

Source:

(资源：)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY test_memdata IS
    PORT (
        address, data : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
        wrenable, clock, rdenable : IN std_logic := '0';
        readout : OUT std_logic_vector(31 DOWNTO 0)
    );
END test_memdata;

ARCHITECTURE arch OF test_memdata IS
    TYPE ram_type IS ARRAY(0 TO 31) OF std_logic_vector(31 DOWNTO 0);
    SIGNAL ram_block : ram_type;
BEGIN
    process(clock, wrenable, address)  
        variable write_addr : integer;
        variable write_en, read_en : std_logic;
    begin
        write_en := wrenable;
        read_en := rdenable;
        write_addr := to_integer(unsigned(address));
        if rising_edge(clock) then
            if write_en = '1' then
                ram_block(write_addr) <= data;
            elsif read_en = '1' then
                readout <= ram_block(write_addr);
            end if;
        end if;
    end process;
END arch;

Modelsim Testbench

(Modelsim测试平台)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY memdata_test IS
END memdata_test;
ARCHITECTURE arch OF memdata_test IS
    SIGNAL address, data : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
    SIGNAL wrenable, clock, rdenable : std_logic := '0';
    SIGNAL readout : std_logic_vector(31 DOWNTO 0);
    COMPONENT test_memdata IS
        PORT (
            address, data : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
            wrenable, clock, rdenable : IN std_logic := '0';
            readout : OUT std_logic_vector(31 DOWNTO 0)
        );
    END COMPONENT test_memdata;
BEGIN
    uut : test_memdata PORT MAP(
        address => address,
        data => data,
        wrenable => wrenable,
        rdenable => rdenable,
        clock => clock,
        readout => readout
    );

    PROCESS
    BEGIN
        address <= (OTHERS => '0');
        data <= (OTHERS => '1');
        WAIT FOR 200 ns;
        clock <= '1';
        wrenable <= '1';
        WAIT FOR 200 ns;
        clock <= '0';
        wrenable <= '0';
        WAIT FOR 200 ns;
        clock <= '1';
        rdenable <= '1';
        WAIT FOR 200 ns;
        REPORT "end";
        WAIT;
    END PROCESS;
END arch;

In ModelSim, this testbench works as expected:

(在ModelSim中，此测试平台按预期工作：) But in Quartus, it doesn't work as expected for some reason:

(但是在Quartus中，由于某些原因，它无法按预期工作：)

But if I extend the rden and wren before the clock signal rising edges, it works:

(但是，如果我在时钟信号上升沿之前延长rden和wren ，它将起作用：)

I've been at this for a very long time, and would really appreciate some insight as to how I would be able to make the read/write happen when both wrenable / rdenable and clock are positive edged at the same time.

(我从事此工作已经很长时间了，如果在wrenable / rdenable和clock处于正rdenable时如何进行读写，我将不胜感激。)

Thank you.

(谢谢。)

ModelSim-Altera 10.1d, Quartus version 13.0sp1

(ModelSim-Altera 10.1d，Quartus版本13.0sp1)

  ask by platizin translate from so

Answer 1

Your memory model is wrong, you should only use one event which is the clock edge so remove the wrenable and address from your process sensitivity list, there is also no need for the 3 variables.

(您的内存模型是错误的，您仅应使用一个事件（即时钟沿），因此从进程敏感度列表中删除可悲的地址，并且不需要这3个变量。)

Good luck,

(祝好运，)

Hans.

(汉斯)