vhdl - "GT0 is not compiled in xil_defaultlib" and "gt is not declared"

Question

this is my first time working in VHDL, and I was wondering why I am getting an error of "gt1 is not compiled in library 'xil_defaultlib', and 'gt is not declared' in struc_arch. The purpose of the code is to basically have a 2 bit comparator that will output 1 if a is greater than b.

architecture struc_arch of gt2 is
    signal g1 : std_logic;
begin
    gt_bit0_unit : entity work.gt0(sop_arch)
        port map(
            i0 => a(1),
            i1 => b(0),
            gt => g0
        );
    agtb <= gt;
end struc_arch;

And the code of the sop_arch that is referenced:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity gt2 is
port (a,b : in std_logic_vector(1 downto 0);
agtb : out std_logic);
end gt2;

architecture sop_arch of gt2 is
begin
agtb <= '1' when (a>b) else
'0';
end sop_arch;

question from:https://stackoverflow.com/questions/66048991/gt0-is-not-compiled-in-xil-defaultlib-and-gt-is-not-declared

Answer 1

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