vhdl - Reset of FIFO (Asynchronous or Synchronous) obtained during instantiating FIFO from IP core of XILINX ISE is active low or active high?

Question

I am using FIFO from IP core generator, which is BRAM-based operating at a common clock for reading and write and the reset type is asynchronous.I want to know the type of this asynchronous reset whether it is active high or active low. Is the reset type is fixed by the IP core generator or we can use as per our need?

question from:https://stackoverflow.com/questions/66046619/reset-of-fifo-asynchronous-or-synchronous-obtained-during-instantiating-fifo-f

Answer 1

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