sdk - Xilinx - Vivado Project: VGA IO not working

Question

I'm new to Xilinx-Vivado. So at the moment we just need to look and see how Vivado and SDK work using Zybo Zynq-7000 Board. I searched on the internet, and found a project with VGA IO. The mysterious thing is that I actually made it to work when I was at school, but due to the current situation, we are not able to get much help, I am now alone with it at home.

This is the project.

Firstly I'd like to ask what does the console below tell me?

1. I generated the bitstream, and then exported the hardware included the bitstream, lastly I launch SDK. On SDK i programmed the FPGA and then ran the project as Launch as Hardware (System debugger and GDB). That's how I did it: Image1

2. And the configuartions: Image2

3. And the output I am getting through the console is: Image3

To my main problem, it is that I have connected all the cables to the Zybo Board that is required; USB cable from my laptop to the FPGA and VGA cable from the FPGA up to my monitor screen. The problem is that I am not getting any output on my monitor, do I have to enable something so that my VGA cable from FPGA to monitor is working?

question from:https://stackoverflow.com/questions/65600098/xilinx-vivado-project-vga-io-not-working

Answer 1

This ultimately boils down to standard debugging. I can only give a couple suggestions.

First, confirm that your design is working in simulation; check that your outputs, especially your sync signals, are working as expected.

Next confirm that your IO constraints are set up correctly and that you are using the right IO pins on the board.

If those all seem correct, ideally you'd have access to a signal analyzer, but that sounds unlikely in current circumstances. As an alternative, you can look at using an ILA, like chipscope, to probe the signals and see monitor them in hardware.

Last, and obviously, make sure all of the cables are connected correctly.

Good luck with the design.