vhdl - Using std_logic_vector with logical operators

Question

I'm trying to use logical operators on an std_logic_vector signal and an std_logic signal, and get an output of either logic 1 (high) or logic 0 (low) and place it in room1 signal

entity sample is
   port(
       source: in std_logic_vector(2 downto 0);
       sw1: in std_logic;
       sw2: in std_logic;
       room1: out std_logic;
       room2: out std_logic
  );
end entity;

architecture behv of sample is
begin
  process (source, sw1, sw2)
  begin
    room1 <= (source="01" and sw1);
  wait for 10 ns;

end behv;

However, I'm getting errors. I'm new to vhdl, how is this done? Thank you!

question from:https://stackoverflow.com/questions/65929565/using-std-logic-vector-with-logical-operators

Answer 1

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