matrix - Test bench for a array of input system verilog

Question

Can someone please help me with the testbench for this code? This seems to work correct with a 10X10 matrix but as I increase the size of the matrix to 20X20 it seems to get stuck at 0fs. I would need the entire 20X20 matrix to be present as an input. I do not want to send the input as 1 bit by 1 bit, in reality the entire input will already be available in the memory and i want to use this only for simulation purpose.

module twenty(input clk, input [0:31] rad[0:39][0:39],
output logic [0:31] iradd[0:19][0:19]);
reg [0:31]irad [0:19][0:19];
logic [0:31]rad [0:19][0:19];


reg [0:31] EL0[0:1];
reg [0:31] EL1[0:1];
reg [0:31] EL2[0:1];
reg [0:31] EL3[0:1];
reg [0:31] EL4[0:1];
reg [0:31] EL5[0:1];
reg [0:31] EL6[0:1];
reg [0:31] EL7[0:1];
reg [0:31] EL8[0:1];
reg [0:31] EL9[0:1];
reg [0:31] EL10[0:1];
reg [0:31] EL11[0:1];
reg [0:31] EL12[0:1];
reg [0:31] EL13[0:1];
reg [0:31] EL14[0:1];
reg [0:31] EL15[0:1];
reg [0:31] EL16[0:1];
reg [0:31] EL17[0:1];
reg [0:31] EL18[0:1];
reg [0:31] EL19[0:1];
reg [0:31] EL20[0:1];
reg [0:31] EL21[0:1];
reg [0:31] EL22[0:1];
reg [0:31] EL23[0:1];
reg [0:31] EL24[0:1];
reg [0:31] EL25[0:1];
reg [0:31] EL26[0:1];
reg [0:31] EL27[0:1];
reg [0:31] EL28[0:1];
reg [0:31] EL29[0:1];
reg [0:31] EL30[0:1];
reg [0:31] EL31[0:1];
reg [0:31] EL32[0:1];
reg [0:31] EL33[0:1];
reg [0:31] EL34[0:1];
reg [0:31] EL35[0:1];
reg [0:31] EL36[0:1];
reg [0:31] EL37[0:1];
reg [0:31] EL38[0:1];
reg [0:31] EL39[0:1];


reg[0:31]ELL1[0:1];
reg[0:31]ELL2[0:1];
reg [0:31]mxm;
reg [0:31]st;
integer i,j,vall,roww,coll,k,p,v,b,f,t;
integer y1,y2,x1,x2,x,y,m1,m2,c1,c2,c3,c4,c5,c6,c7,c8,c9;

always@(*)
begin

EL0[0]= 32'd0;
EL0[1]= 32'd0;
EL1[0]= 32'd0;
EL1[1]= 32'd1;
EL2[0]= 32'd0;
EL2[1]= 32'd3;
EL3[0]= 32'd0;
EL3[1]= 32'd5;
EL4[0]= 32'd0;
EL4[1]= 32'd7;
EL5[0]= 32'd0;
EL5[1]= 32'd9;
EL6[0]= 32'd0;
EL6[1]= 32'd11;
EL7[0]= 32'd0;
EL7[1]= 32'd13;
EL8[0]= 32'd0;
EL8[1]= 32'd15;
EL9[0]= 32'd0;
EL9[1]= 32'd17;
EL10[0]= 32'd0;
EL10[1]= 32'd19;
EL11[0]= 32'd1;
EL11[1]= 32'd19;
EL12[0]= 32'd3;
EL12[1]= 32'd19;
EL13[0]= 32'd5;
EL13[1]= 32'd19;
EL14[0]= 32'd7;
EL14[1]= 32'd19;
EL15[0]= 32'd9;
EL15[1]= 32'd19;
EL16[0]= 32'd11;
EL16[1]= 32'd19;
EL17[0]= 32'd13;
EL17[1]= 32'd19;
EL18[0]= 32'd15;
EL18[1]= 32'd19;
EL19[0]= 32'd17;
EL19[1]= 32'd19;
EL20[0]= 32'd19;
EL20[1]= 32'd19;
EL21[0]= 32'd19;
EL21[1]= 32'd17;
EL22[0]= 32'd19;
EL22[1]= 32'd15;
EL23[0]= 32'd19;
EL23[1]= 32'd13;
EL24[0]= 32'd19;
EL24[1]= 32'd11;
EL25[0]= 32'd19;
EL25[1]= 32'd9;
EL26[0]= 32'd19;
EL26[1]= 32'd7;
EL27[0]= 32'd19;
EL27[1]= 32'd5;
EL28[0]= 32'd19;
EL28[1]= 32'd3;
EL29[0]= 32'd19;
EL29[1]= 32'd1;
EL30[0]= 32'd19;
EL30[1]= 32'd0;
EL31[0]= 32'd17;
EL31[1]= 32'd0;
EL32[0]= 32'd15;
EL32[1]= 32'd0;
EL33[0]= 32'd13;
EL33[1]= 32'd0;
EL34[0]= 32'd11;
EL34[1]= 32'd0;
EL35[0]= 32'd9;
EL35[1]= 32'd0;
EL36[0]= 32'd7;
EL36[1]= 32'd0;
EL37[0]= 32'd5;
EL37[1]= 32'd0;
EL38[0]= 32'd3;
EL38[1]= 32'd0;
EL39[0]= 32'd1;
EL39[1]= 32'd0;


for(i = 0; i<= 19; i++)
begin
for( j = 0; j<= 19; j++)
begin
irad[i][j] = 32'd0;
iradd[i][j] = 32'd0;
end
end



for(i = 0; i< 39; i++)
begin
for( j = 0; j< 39; j++)
begin
if( rad[i][j] != 0)
begin
vall = rad[i][j];
roww = i;
coll = j;


case(roww)
0 :begin
ELL1[0] = EL0[0];
ELL1[1] = EL0[1];
end
1 :begin
ELL1[0] = EL1[0];
ELL1[1] = EL1[1];
end
2 :begin
ELL1[0] = EL2[0];
ELL1[1] = EL2[1];
end
3 :begin
ELL1[0] = EL3[0];
ELL1[1] = EL3[1];
end
4 :begin
ELL1[0] = EL4[0];
ELL1[1] = EL4[1];
end
5 :begin
ELL1[0] = EL5[0];
ELL1[1] = EL5[1];
end
6 :begin
ELL1[0] = EL6[0];
ELL1[1] = EL6[1];
end
7 :begin
ELL1[0] = EL7[0];
ELL1[1] = EL7[1];
end
8 :begin
ELL1[0] = EL8[0];
ELL1[1] = EL8[1];
end
9 :begin
ELL1[0] = EL9[0];
ELL1[1] = EL9[1];
end
10 :begin
ELL1[0] = EL10[0];
ELL1[1] = EL10[1];
end
11 :begin
ELL1[0] = EL11[0];
ELL1[1] = EL11[1];
end
12 :begin
ELL1[0] = EL12[0];
ELL1[1] = EL12[1];
end
13 :begin
ELL1[0] = EL13[0];
ELL1[1] = EL13[1];
end
14 :begin
ELL1[0] = EL14[0];
ELL1[1] = EL14[1];
end
15 :begin
ELL1[0] = EL15[0];
ELL1[1] = EL15[1];
end
16 :begin
ELL1[0] = EL16[0];
ELL1[1] = EL16[1];
end
17 :begin
ELL1[0] = EL17[0];
ELL1[1] = EL17[1];
end
18 :begin
ELL1[0] = EL18[0];
ELL1[1] = EL18[1];
end
19 :begin
ELL1[0] = EL19[0];
ELL1[1] = EL19[1];
end
20 :begin
ELL1[0] = EL20[0];
ELL1[1] = EL20[1];
end
21 :begin
ELL1[0] = EL21[0];
ELL1[1] = EL21[1];
end
22 :begin
ELL1[0] = EL22[0];
ELL1[1] = EL22[1];
end
23 :begin
ELL1[0] = EL23[0];
ELL1[1] = EL23[1];
end
24 :begin
ELL1[0] = EL24[0];
ELL1[1] = EL24[1];
end
25 :begin
ELL1[0] = EL25[0];
ELL1[1] = EL25[1];
end
26 :begin
ELL1[0] = EL26[0];
ELL1[1] = EL26[1];
end
27 :begin
ELL1[0] = EL27[0];
ELL1[1] = EL27[1];
end
28 :begin
ELL1[0] = EL28[0];
ELL1[1] = EL28[1];
end
29 :begin
ELL1[0] = EL29[0];
ELL1[1] = EL29[1];
end
30 :begin
ELL1[0] = EL30[0];
ELL1[1] = EL30[1];
end
31 :begin
ELL1[0] = EL31[0];
ELL1[1] = EL31[1];
end
32 :begin
ELL1[0] = EL32[0];
ELL1[1] = EL32[1];
end
33 :begin
ELL1[0] = EL33[0];
ELL1[1] = EL33[1];
end
34 :begin
ELL1[0] = EL34[0];
ELL1[1] = EL34[1];
end
35 :begin
ELL1[0] = EL35[0];
ELL1[1] = EL35[1];
end
36 :begin
ELL1[0] = EL36[0];
ELL1[1] = EL36[1];
end
37 :begin
ELL1[0] = EL37[0];
ELL1[1] = EL37[1];
end
38 :begin
ELL1[0] = EL38[0];
ELL1[1] = EL38[1];
end
39 :begin
ELL1[0] = EL39[0];
ELL1[1] = EL39[1];
end


default :begin
ELL1[0] = EL0[0];
ELL1[1] = EL0[1];
end
endcase

case(coll)
0 :begin
ELL2[0] = EL0[0];
ELL2[1] = EL0[1];
end
1 :begin
ELL2[0] = EL1[0];
ELL2[1] = EL1[1];
end
2 :begin
ELL2[0] = EL2[0];
ELL2[1] = EL2[1];
end
3 :begin
ELL2[0] = EL3[0];
ELL2[1] = EL3[1];
end
4 :begin
ELL2[0] = EL4[0];
ELL2[1] = EL4[1];
end
5 :begin
ELL2[0] = EL5[0];
ELL2[1] = EL5[1];
end
6 :begin
ELL2[0] = EL6[0];
ELL2[1] = EL6[1];
end
7 :begin
ELL2[0] = EL7[0];
ELL2[1] = EL7[1];
end
8 :begin
ELL2[0] = EL8[0];
ELL2[1] = EL8[1];
end
9 :begin
ELL2[0] = EL9[0];
ELL2[1] = EL9[1];
end
10 :begin
ELL2[0] = EL10[0];
ELL2[1] = EL10[1];
end
11 :begin
ELL2[0] = EL11[0];
ELL2[1] = EL11[1];
end
12 :begin
ELL2[0] = EL12[0];
ELL2[1] = EL12[1];
end
13 :begin
ELL2[0] = EL13[0];
ELL2[1] = EL13[1];
end
14 :begin
ELL2[0] = EL14[0];
ELL2[1] = EL14[1];
end
15 :begin
ELL2[0] = EL15[0];
ELL2[1] = EL15[1];
end
16 :begin
ELL2[0] = EL16[0];
ELL2[1] = EL16[1];
end
17 :begin
ELL2[0] = EL17[0];
ELL2[1] = EL17[1];
end
18 :begin
ELL2[0] = EL18[0];
ELL2[1] = EL18[1];
end
19 :begin
ELL2[0] = EL19[0];
ELL2[1] = EL19[1];
end
20 :begin
ELL2[0] = EL20[0];
ELL2[1] = EL20[1];
end
21 :begin
ELL2[0] = EL21[0];
ELL2[1] = EL21[1];
end
22 :begin
ELL2[0] = EL22[0];
ELL2[1] = EL22[1];
end
23 :begin
ELL2[0] = EL23[0];
ELL2[1] = EL23[1];
end
24 :begin
ELL2[0] = EL24[0];
ELL2[1] = EL24[1];
end
25 :begin
ELL2[0] = EL25[0];
ELL2[1] = EL25[1];
end
26 :begin
ELL2[0] = EL26[0];
ELL2[1] = EL26[1];
end
27 :begin
ELL2[0] = EL27[0];
ELL2[1] = EL27[1];
end
28 :begin
ELL2[0] = EL28[0];
ELL2[1] = EL28[1];
end
29 :begin
ELL2[0] = EL29[0];
ELL2[1] = EL29[1];
end
30 :begin
ELL2[0] = EL30[0];
ELL2[1] = EL30[1];
end
31 :begin
ELL2[0] = EL31[0];
ELL2[1] = EL31[1];
end
32 :begin
ELL2[0] = EL32[0];
ELL2[1] = EL32[1];
end
33 :begin
ELL2[0] = EL33[0];
ELL2[1] = EL33[1];
end
34 :begin
ELL2[0] = EL34[0];
ELL2[1] = EL34[1];
end
35 :begin
ELL2[0] = EL35[0];
ELL2[1] = EL35[1];
end
36 :begin
ELL2[0] = EL36[0];
ELL2[1] = EL36[1];
end
37 :begin
ELL2[0] = EL37[0];
ELL2[1] = EL37[1];
end
38 :begin
ELL2[0] = EL38[0];
ELL2[1] = EL38[1];
end
39 :begin
ELL2[0] = EL39[0];
ELL2[1] = EL39[1];
end

default :begin
ELL2[0] = EL0[0];
ELL2[1] = EL0[1];
end
endcase


x1 = ELL1[0];
y1 = ELL1[1];
x2 = ELL2[0];
y2 = ELL2[1];
m1 = ((y2-y1)/(x2-x1));
for(y = 0; y<= 19;y++)
begin
for(x = 0;x<= 19;x++)
begin

m2 = ((y1-y)/(x1-x));
c1=(m1==m2);
c2=((y1<y)&&(y<y2));
c3=((x1<x)&&(x<x2));
c4=((y2<y)&&(y<y1));
c5=((x2<x)&&(x<x1));
c6=((x1==x)&&(x2==x));
c7=((y1==y)&&(y2==y));
c8=((x1==x)&&(y1==y));
c9=((x2==x)&&(y2==y));

if ( c1 && (c2||c4) && (c3||c5) )
begin
//$display("slopes are equal");
irad[x][y]=irad[x][y]+vall;
end
else if ( c6 && (c2 || c4))
begin
//$display("point is on the line ");
irad[x][y]=irad[x][y]+vall;
end
else if ( c7 && (c3 || c5))
begin
//$display("point is on the line ");
irad[x][y]=irad[x][y]+vall;
end
else if ( c8 || c9 )
begin
//$display("electrode is also a point");
irad[x][y]=irad[x][y]+vall;
end
else $display("not present");
end
end


end
end
end
mxm= 32'd0;
st=32'd0;
for( k = 0; k<= 19; k = k+1)
begin
for( p = 0; p<= 19; p = p+1)
begin
st = irad[k][p];
if (st > mxm)
begin
mxm = st;
end
end
end
for( f = 0; f<= 19; f= f+1)
begin
for( t = 0; t<= 19; t = t+1)
begin
st = irad[f][t];
iradd[f][t] = (st);
end
end
end
endmodule

Test Bench

module twenty_tb();
logic [0:31] iradd [0:19][0:19];
logic [0:31]rad [0:39][0:39];
logic [0:31]RAM [0:39][0:39];
integer a,b;
integer i,j;
reg clk;
initial
begin
clk = 1'b1;

end
twenty twenty_inst(.clk(clk), .rad(rad),.iradd(iradd));

always@(posedge clk)
begin
$readmemh("C:/Users/WS2-Praseetha/Desktop./RAM.txt", RAM);



$display("data:");
for (i=0; i < 40 ; i=i+1)
begin
for (j=0; j < 40; j=i+1)
begin
$display("%d:%d:%d",i,j,RAM[i][j]);
end
end

end
initial
begin


for (i=0; i < 40; i=i+1)
begin
for (j=0; j < 40; j=i+1)
begin
a = RAM[i][j];
b = RAM[j][i];
if((a == b) && (a!=0))
begin
RAM[j][i] = 31'd0;
rad[i][j] = RAM[i][j];
end
else
begin
rad[i][j] = RAM[i][j];
end
end
end

//$monitor("rad = %d, iradd = %d",$rad,iradd);

end


endmodule

question from:https://stackoverflow.com/questions/65898936/test-bench-for-a-array-of-input-system-verilog

Answer 1

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