blocking - SystemVerilog calculations right before writing to clocking block

Question

I have a task, whose job it is to drive data onto a bus via a clocking block. See snippet:

task effects_driver::ReadQueueData();
  stream_intf_.cycles(); // clocking block event
  if (sample_q_.size() >= 2) // check to see if there is enough data in the queue
    begin
      automatic bit [31:0] sample0, sample1;
      sample0 = sample_q_.pop_front(); // read from queue
      sample1 = sample_q_.pop_front(); // read from queue
      stream_intf_.cb.AXIS_TDATA <= {sample1, sample0}; // drive two samples at once
      stream_intf_.cb.AXIS_TVALID <= 1;
    end
  else
    ...
endtask

You'll notice that I need to read a couple of items out of a queue before writing it to the clocking block. Is this the correct way to do it? Am I guaranteed that the simulator will perform these blocking assignments to the automatic variable before writing it to the clocking block?

Thanks!

P.S. I run into this scenario semi-frequently--where I need to do some quick calculations on the fly right before writing to the clocking block.

question from:https://stackoverflow.com/questions/65890521/systemverilog-calculations-right-before-writing-to-clocking-block

Answer 1

I believe you meant to ask "Am I guaranteed that the simulator will perform these blocking assignments to the automatic variable before writing it to the clocking block?" because that is what your code is doing.

The answer to that is yes, blocking assignments are guaranteed to complete before executing the statement following it.

Also note that there is no need to declare sample0 and sample1 with automatic lifetimes because class methods always have automatic lifetimes. Variables declared within them are implicitly automatic.