verilog - I don't understand this define macro with replication

Question

I have SystemVerilog code in which replication is used that I don't understand. Please be thorough with your answer.

parameter WIDTH = 6;
logic [WIDTH-1:0] flag, flag2;

`define ZERO_X(n, m) {{m-$bits(n){1'b0}}, (n)}

assign flag = flag2 - `ZERO_X(1'b1, WIDTH);

question from:https://stackoverflow.com/questions/65836185/i-dont-understand-this-define-macro-with-replication

Answer 1

The first step is to perform simple text substitution in this expression. Replace n with 1'b1 and m with WIDTH. So this:

`ZERO_X(1'b1, WIDTH)

becomes:

{{WIDTH-$bits(1'b1){1'b0}}, (1'b1)}

Replace WIDTH with 6:

{{6-$bits(1'b1){1'b0}}, 1'b1}

$bits(1'b1) evaluates to 1:

{{(6-1){1'b0}}, 1'b1}

6-1 is just 5:

{{5{1'b0}}, 1'b1}

{5{1'b0}} replicates 1'b0 out to 5 0's:

{5'b0_0000, 1'b1}

Then simple concatenation:

6'b00_0001

Thus, this line:

assign flag = flag2 - `ZERO_X(1'b1, WIDTH);

evaluates to:

assign flag = flag2 - 6'b00_0001;