hdl - How does adding 1'b1 to 8 bit reg work in Verilog?

Question

I am absolute beginner in Verilog and I am wondering how does the addition statement work in this piece of program.

reg [7:0] hcount;
...
always @(posedge clk) begin
      if(!n_rst) begin
         hcount <= 'd0;
      end else if(hcount== (WIDTH-1)) begin
         hcount <= 'd0;
      end else begin
         hcount <= hcount + 1'b1;
      end
   end

I understand that 1'b1 expands to 8'b1 because hcount has 8 bit width and now the calculation will work with 8 bit now. But how exactly does that addition work? Your help is much appreciated.

question from:https://stackoverflow.com/questions/65831675/how-does-adding-1b1-to-8-bit-reg-work-in-verilog

Answer 1

Verilog is a hardware description langue in a sense that it tries to describe behavior of real hardware. One of attributes of modern hardware is clock. Clock drives flops which synchronize data across different hardware devices.

Clock behavior in verilog is simulated by posedge clk (or negede), meaning that the corresponding always block will be executed if and only if clk switches to 1 from any other value (x, z, 0);.

So, in your case, there is supposed to be a clock (clk) which gets generated somewhere in test bench. It periodically switches between 0 and 1.

As soon as it switches 0 -> 1 it gets executed. If condition is right, the hcount <= hcount + 1'b1 will be executed. As you mentioned the compiler will zero-extend 1'b1 to the 8-bit value 00000001. The rest is the same as in any programming language, hcount will be incremented.

There is certain semantic associated with the non-blocking assignment, <=, but this would be a different question. For the purpose of your question it does not matter.

So, a result will be that a single increment will be done every clock cycle unless n_rst is '0'. Also, as soon as the counter reaches WIDH - 1 it will be set to '0'. Only one operation is allowed at a single clock edge.