Can anyone help me create a testbench or just the input code for my following code? I'm using XILINX.
module fsmb (input rst,clk,a,
output reg x);
parameter sta = 2'b00, stb = 2'b01, stc = 2'b10,
std = 2'b11;
reg[1:0] st, nst;
always @(posedge clk)
begin
if (rst)
st <= 2'b00;
else
st <= nst;
end
always @*
begin
st = nst; x =0'b0;
case (st)
sta: if(a) nst = stb;
else nst = sta;
stb: if(a) nst = stc;
else nst = stb;
stc: begin
if(a) nst = stc;
else nst = std;
x =1'b1;
end
std: begin
if(a) nst = stc;
else nst = sta;
x = 1'b1;
end
default: nst = sta;
endcase
end
endmodule
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