computer architecture - word size and data bus

Question

I am confused about the definition of word size. I read that the word size of a processor is its data bus width. Like an 8 bit processor has an 8 bit wide data bus. I recently read that the maximum size of the virtual address space is determined by word size i.e. if the word size is n bits the max virtual address space is 2^n -1. But I always thought that maximum virtual address space is determined by address bus width i.e. an n bits wide address bus can address maximum 2^n bytes. So, what is true?

Also, is this related to pointers as an n bit data bus is capable of carrying only an n bit address. So, maximum 2^n bytes can be accessed via pointers.

Answer 1

I'll first say that some of your confusion probably comes from the fact that things were simpler a few decades ago and your understanding of terms is based on these simpler machines.

I am confused about the definition of word size.I read that the word size of a processor is its data bus width. Like an 8 bit processor has an 8 bit wide data bus.

Definitely not. Data bus with is completely unrelated to this. The word size (which has never really been a precise term) of a processor is best loosely defined as the largest natural size for arithmetic which is generally the size of the registers in the machine. This is quite frequently the width of the data path (which is distinctly different from the data bus). The data path is simply the width of the ALUs. The word size is often the same as the pointer size.

I recently read that the maximum size of the virtual address space is determined by word size i.e. if the word size is n bits the max virtual address space is 2^n -1. But i always thought that maximum virtual address space is determined by address bus width i.e. an n bits wide address bus can address maximum 2^n bytes. So, what is true?

No. The size of the virtual address space is simply determined by the number of bits in the virtual page number of the page table (and the TLB). On current amd64 based machines, only 48 bits of the virtual address are useable. The upper 16 are a sign extension of bit 47. On current amd64 machines, the physical address size is 52 bits. These physical address bits are the ones that are sent on the bus. Though even the term bus is really incorrect. Almost all links are point-to-point (DDRx DRAM is an exception) and use a packetized format (header + payload) instead of address wires and data wires.

Also, is this related to pointers as an n bit data bus is capable of carrying only an n bit address. So, maximum 2^n bytes can be accessed via pointers.

Many (almost all even) machines that have a separate address bus, use an address bus that is narrower than the the number of address bits. These bits are simply split up and sent across the bus using multiple clock cycles. DDRx DRAM is another example of this.