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Recent questions tagged vhdl
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vhdl - shift a std_logic_vector of n bit to right or left
I have a vector signal tmp : std_logic_vector(15 downto 0) I have to shift it to left or right of n bit. how can ... I didn't know how use it. See Question&Answers more detail:os...
asked
Oct 17, 2021
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vhdl
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509
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vhdl - Using std_logic_vector with logical operators
I'm trying to use logical operators on an std_logic_vector signal and an std_logic signal, and get an ... com/questions/65929565/using-std-logic-vector-with-logical-operators...
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Oct 7, 2021
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vhdl
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441
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vhdl - How to access implicit "=" function for an array type when it is overloaded in the same package?
I had a sudden thought. Is it possible to access the implicit "=" function for an array type when an overload ... implicit-function-for-an-array-type-when-it-is-overloaded-in-t...
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Oct 7, 2021
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vhdl
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606
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answer
vhdl - clk'event vs rising_edge()
I had always used this for detecting a rising edge: if (clk'event and clk='1') then but this can ... from:https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge...
asked
Oct 7, 2021
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vhdl
0
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840
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vhdl - clk'event vs rising_edge()
I had always used this for detecting a rising edge: if (clk'event and clk='1') then but this can ... from:https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge...
asked
Oct 7, 2021
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71.8m
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vhdl
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534
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vhdl - Reset of FIFO (Asynchronous or Synchronous) obtained during instantiating FIFO from IP core of XILINX ISE is active low or active high?
I am using FIFO from IP core generator, which is BRAM-based operating at a common clock for reading ... -of-fifo-asynchronous-or-synchronous-obtained-during-instantiating-fifo-f...
asked
Oct 6, 2021
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vhdl
0
votes
582
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answer
vhdl - Error: Signal parameter requires signal expression on function call
Short question: I've written a function that takes a signal integer as parameter. The compiler throws the ... /error-signal-parameter-requires-signal-expression-on-function-call...
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Oct 6, 2021
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71.8m
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vhdl
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1.1k
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1
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vhdl - "GT0 is not compiled in xil_defaultlib" and "gt is not declared"
this is my first time working in VHDL, and I was wondering why I am getting an error of "gt1 is not compiled in ... /gt0-is-not-compiled-in-xil-defaultlib-and-gt-is-not-declared...
asked
Oct 6, 2021
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vhdl
0
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544
views
1
answer
vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)
I am trying to create a simple memory that stores vectors whenever the clock is 1 and wrenable is 1 (and likewise ... 10.1d,Quartus版本13.0sp1) ask by platizin translate from so...
asked
Mar 6, 2021
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vhdl
0
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552
views
1
answer
vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)
I am trying to create a simple memory that stores vectors whenever the clock is 1 and wrenable is 1 (and likewise ... 10.1d,Quartus版本13.0sp1) ask by platizin translate from so...
asked
Mar 6, 2021
in
Technique[技术]
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深蓝
(
71.8m
points)
vhdl
0
votes
512
views
1
answer
vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)
I am trying to create a simple memory that stores vectors whenever the clock is 1 and wrenable is 1 (and likewise ... 10.1d,Quartus版本13.0sp1) ask by platizin translate from so...
asked
Mar 6, 2021
in
Technique[技术]
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深蓝
(
71.8m
points)
vhdl
0
votes
526
views
1
answer
vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)
I am trying to create a simple memory that stores vectors whenever the clock is 1 and wrenable is 1 (and likewise ... 10.1d,Quartus版本13.0sp1) ask by platizin translate from so...
asked
Feb 21, 2021
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71.8m
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vhdl
0
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567
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1
answer
vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)
I am trying to create a simple memory that stores vectors whenever the clock is 1 and wrenable is 1 (and likewise ... 10.1d,Quartus版本13.0sp1) ask by platizin translate from so...
asked
Feb 21, 2021
in
Technique[技术]
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71.8m
points)
vhdl
0
votes
540
views
1
answer
vhdl - waveform does not work properly for some operations
i am newbie in vhdl, modelsim, waveform etc. i've developed a simple operational process and a testbench to test my ... 101"; wait; end process; end behave; thanks in advance....
asked
Feb 19, 2021
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71.8m
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vhdl
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votes
916
views
1
answer
vhdl - Intel Quartus Error 12002 Port does not exist in macrofunction
Working with an Intel Cyclone 10 FPGA and running into a compile error I cannot seem to debug properly. The errors ... obvious I am missing.. but any help is appreciated....
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Feb 19, 2021
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vhdl
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756
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vhdl - An issue regarding multiple drivers on a wire, error: [DRC MDRV-1] Multiple Driver Nets: Net led_OBUF[0] has multiple drivers: led_OBUF[0]_inst_i_1/O
I am creating a simple VHDL code which should create two 4 bit binary numbers (A and B) using 8 inputs (4 for ... other code. Please could someone help me explain what's going on?...
asked
Feb 6, 2021
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71.8m
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vhdl
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