Recent questions tagged X86

0 votes

582 views

1 answer

x86 64 - How to tell length of an x86-64 instruction opcode using CPU itself?

I know that there are libraries that can "parse" binary machine code / opcode to tell the length of an x86-64 CPU ... code? (Maybe even a hack?) See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

763 views

1 answer

x86 Assembly: Division Floating Point Exception dividing by 11

I'm trying to divide 859091 by 11 to obtain the quotient and the remainder, but I'm getting Floating Point ... exit div bx exit: leave ret See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

819 views

1 answer

x86 16 - Assembly multiplication of 16-bit x 32-bit => 48-bit

Assume I want to multiply a large number by another (maybe small) number in assembly. The big number (multiplicand) ... zero! Any idea on that? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1.1k views

1 answer

x86 - What is the gcc cpu-type that includes support for RDTSCP?

I am using RDTSCP to replace LFENCE;RDTSC sequences and also get the processor ID back so that I know ... cpu family first introduced RDTSCP? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

742 views

1 answer

x86 - Data bus width and word size

Will data bus width size change when word size changes? I think that it will change because data bus width is ... also changes. Am I correct? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

605 views

1 answer

x86 64 - Linux's security measures against executing shellcode

I'm learning the basics of computer security and I'm trying to execute some shellcode I've written. I followed the ... can I get this to work? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

587 views

1 answer

x86 - Write a Fizz program in assembly / Using C library

Could someone help me with this assembly program: First print out numbers 1 to 100. Then follow the rules for the ... 100 jae end inc eax end: See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

978 views

1 answer

x86 64 - How is CR8 register used to prioritize interrupts in an x86-64 CPU?

I'm reading the Intel documentation on control registers, but I'm struggling to understand how CR8 register is used. ... discarded, i.e. lost? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

755 views

1 answer

x86 - Cannot read disk sectors in assembly language

I am trying to read disk sectors by the following code: disk_load : push dx mov ah , 0x02 ; BIOS read ... in Virtual Box if that matters. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

845 views

1 answer

x86 - How to represent octal numbers in Assembly?

For example for hexadecimal numbers we can use 0x98398 or 8790h. How can octal numeric constants be written? Does this work? mov eax, 70o See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

532 views

1 answer

x86 - The most correct way to refer to 32-bit and 64-bit versions of programs

This question is about terminology for 32-bit vs. 64-bit x86. If I have 2 directories with source code of the ... //en.wikipedia.org/wiki/X86-64 See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

752 views

1 answer

x86 - (NASM) (80x86) Bootloader NEEDS xor ax, ax

I am learning how to make a bootloader from osdev. I'm using NASM to assemble my code, and a x86 machine to ... a pen drive Thank you so much. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

546 views

1 answer

x86 assembly 16 bit vs 8 bit immediate operand encoding

I'm writing my own assembler and trying to encode the ADC instruction, I have a question about immediate values ... my approach correct as well? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

778 views

1 answer

x86 - What is the difference between _mm512_load_epi32 and _mm512_load_si512?

The Intel intrinsics guide states simply that _mm512_load_epi32: Load[s] 512-bits (composed of 16 packed 32-bit ... documentation isn't clear. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1.4k views

1 answer

x86 - Regarding cmp / jg, jle, etc in AT&T syntax assembly

So every single resource online tells me that something like this: cmp %eax, %ebx jg < something > would jump ... other jump statements as well? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

516 views

1 answer

x86 - Conditional jump instructions in MSROM procedures?

This relates to this question Thinking about it though, on a modern intel CPU the SEC phase is ... actions are preformed internally. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

518 views

1 answer

x86 64 - Why am I seeing more RFO (Read For Ownership) requests using REP MOVSB than with vmovdqa

Checkout Edit3 I was getting the wrong results because I was measuring without including prefetch triggered ... 30 offcore_requests.demand_rfo 0.166300952 seconds time elapsed...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

819 views

1 answer

x86 - SSE multiplication of 2 64-bit integers

How to multiply two 64-bit integers by another 2 64-bit integers? I didn't find any instruction which can do it. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

708 views

1 answer

x86 - assembly cltq and movslq difference

Chapter 3 of Computer Systems A Programmer's Perspective (2nd Edition) mentions that cltq is equivalent to movslq ... Isn't that redundant? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

860 views

1 answer

x86 - When using a mask register with AVX-512 load and stores, is a fault raised for invalid accesses to masked out elements?

When I do a writemasked AVX-512 store, like so: vmovdqu8 [rsi] {k1}, zmm0 Will the instruction fault ... ability to vmaskmov introduced in AVX. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

764 views

1 answer

x86 64 - Calling C function from x64 assembly with registers instead of stack

This answer puzzled me. According to the standard C calling conventions, the standard way to call C functions ... would be truly appreciated.) See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

558 views

1 answer

x86 - Assembly code to return smallest integer in array instead randomly returns either last or second to last number

I'm trying to create a function in nasm which, given an array of integers and the length of the array, ... I do not really understand why. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

503 views

1 answer

x86 - Was there a P4 model with double-pumped 64-bit operations?

I recall that one of the interesting features of the initial P4 micro-architecture was it's double-pumped ... is interesting for optimization. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

430 views

1 answer

x86 - Why jnz requires 2 cycles to complete in an inner loop

I'm on an IvyBridge. I found the performance behavior of jnz inconsistent in inner loop and outer loop. ... This somehow explains the behavior. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

458 views

1 answer

x86 - The ordering of L1 cache controller to process memory requests from CPU

Under the total store order(TSO) memory consistency model, a x86 cpu will have a write buffer to buffer write ... order as the issue order? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

929 views

1 answer

x86 multi-byte NOP and instruction prefix

As a small recall, the x86 architecture defines 0x0F 0x1F [mod R/M] as a multi-byte NOP. Now I'm ... effect on multi-byte NOP instructions? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

570 views

1 answer

x86 - How does the indexing of the Ice Lake's 48KiB L1 data cache work?

The Intel manual optimization (revision September 2019) shows a 48 KiB 8-way associative L1 data cache for the Ice ... me. What am I missing? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1.1k views

1 answer

x86 - assembly check if number is even

I have homework to write assembly code for checking if number is odd or even. I have this code code_seg SEGMENT ... ) 1 gives result of 0? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

Categories

Just Browsing Browsing

Most popular tags