Recent questions tagged assembly

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assembly - Is there any difference in between (rdtsc + lfence + rdtsc) and (rdtsc + rdtscp) in measuring execution time?

As far as I know, the main difference in runtime ordering in a processor with respect to rdtsc and rdtscp instruction ... ... ... rdtscp lfence See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Passing Arguments C -> NASM -> C

admittedly this is some homework help, but a specific problem I can't seem to get past. I'm trying to write a ... EDX ;restore EDX pop EBP ret See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Intel JCC Erratum - should JCC really be treated separately?

Intel pushed microcode update to fix error called "Jump Conditional Code (JCC) Erratum". The update microcode ... separately from other JCC? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Is mov r64, m64 one cycle or two cycle latency?

I'm on IvyBridge, I wrote the following simple program to measure the latency of mov: section .bss align 64 ... mov latency is still 1 cycle) See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How to populate a 64 bit register with duplicate byte values

I'm doing some x64 assembly with Visual C++ 2010 and masm ('fast call' calling convention). So let's say I ... my compiler, I'm just learning. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Subtracting registers with an LEA instruction?

Does the LEA instruction support negative displacement? mov rax, 1 lea rsi, [rsp - rax] When I use the above ... you in advance for your help! See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Disassembly view of C# 64-bit Release code is 75% longer than 32-bit Debug code?

EDIT I tested release in 32 bit, and the code was compact. Therefore the below is a 64 bit issue. I'm ... bits return (crc ^ 0xffffffff); } See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Get the upper half of the EAX register

In x86 assembly language, is there any way to obtain the upper half of the EAX register? I know that the AX ... of eax into bx as well. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Understanding TLB from CPUID results on Intel

I'm exploring leaf 0x02 of the cpuid instruction and came up with a few questions. There is a table in the ... is the TLB cache core private? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How to detect architecture in NASM at compile time to have one source code for both x64 and x86?

I am looking for some preprocessor functionality in nasm that would allow having one source code for both x86 ... same for both architectures. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - LOOP, LOOPE, LOOPNE?

What's the difference between the assembly instructions LOOP, LOOPE and LOOPNE? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - What are the 128-bit to 512-bit registers used for?

After looking at a table of registers in the x86/x64 architecture, I noticed that there's a whole section of ... in order to manipulate them? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How does the instruction decoder differentiate between EVEX prefix and BOUND opcode in 32-bit mode?

In 32-bit mode Intel solves the VEX prefix vs LDS/LES conflict by inverting the high bits of register extension, ... Which of them is correct? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Is a shift instruction faster than an IMUL instruction?

Which one is faster - val = val*10; or val = (val<<3) + (val<<2); How many clock cycles does imul take when compared to shift instruction? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - :lower16, :upper16 for aarch64; absolute address into register;

I need to put a 32-bit absolute address into a register on AArch64. (e.g. an MMIO address, not PC-relative). ... , but I'd rather avoid that. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Multiplying two values and printing them to the screen (NASM, Linux)

I keep reading that in order for one to perform integer/floating point division on a register, the register(s) ... it technically doesn't 'ret' See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly binding redirect - F# PowerPack Target Runtime

The pre-built binaries for the F# PowerPack are compiled against the .NET 2.0 runtime. If I have a .NET 4.0 ... source for the .NET 4 runtime? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Get argv[2] address in assembler x64

edi is argc, rsi is argv 0x0000000000400535 <+8>: mov %edi,-0x4(%rbp) 0x0000000000400538 <+11>: mov %rsi,-0x10(%rbp ... r10, [r9+0x10] jmp r10 See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Reverse byte order in XMM or YMM register?

Let's say I want to reverse the byte order of a very large byte array. I can do this the slow way using ... order in an XMM or YMM register? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Why MOV AH,1 is not supported in 64 bit mode of intel microprocessor?

In the book "THE INTEL MICROPROCESSORS" of Barry B. Brey, it is written that MOV AH, 1 is not allowed in 64 ... the problem with MOV AH, 1 ? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - x86-64: Cache load and eviction instruction

For x86-64 architecture, is there an instruction that can load data at a given memory address to the cache? ... like a cache line identifier)? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How to interpret this address -0x80(%rbp,%rax,4)

I'm currently trying to learn assembly language (and the effects of different compiler options) by analyzing simple C ... local array in a loop. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - how can i read value from register using C++

I am writhing code with C++ for a calculator ,but it display ead results with assembly,I want to store the value ... find it with C language ... See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - ARM: Is "STMDB SP!, {R0-R8}" (aka PUSH {R0-R8}) an atomic operation?

I wonder if STMDB SP!, {R0-R8} is an atomic operation in ARM(v7), because it looks quite complex to ... processor continues with R0-R4? Thanks. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How to load memory address without using pseudo-instructions?

I'm trying to learn MIPS assembly language by myself using MARS simulator. For didactic reasons I'm limiting myself ... How? Thanks in advance! See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Why do we need stack allocation when we have a red zone?

I have the following doubts: As we know System V x86-64 ABI gives us about a fixed-size area (128 bytes) in ... -1024], rcx add rsp, 1024 ret See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How can linux boot code be written in C?

I'm a newbie to learning OS development. From the book I read, it said that boot loader will copy first MBR into ... but I can't see the detail. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Is the i386 instruction "div ah" pointless?

From https://www.felixcloutier.com/x86/div: ... temp ← AX / SRC; IF temp > FFH THEN #DE; (* Divide error ... over FFH Do I miss something here? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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