Recent questions tagged verilog

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verilog - How to perform right shifting binary multiplication?

This is a homework problem which I tried to solve by myself but I couldn't. The homework is to implement a ... I can implement it by myself. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Eliminating unused bits: creating synthesisable multidimensional arrays of with different dimensions

This is a follow-on question from How can I iteratively create buses of parameterized size to connect modules also ... readable and debug-able? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - How to define a parameterized multiplexer using SystemVerilog

I am trying to create a module which switches x input data packets to a single output packet according to a one ... I define all cases? Thanks. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - better way of coding a D flip-flop

Recently, I had seen some D flip-flop RTL code in verilog like this: module d_ff( input d, input clk, input ... statement q <= q; necessary? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Can we have an array of custom modules?

Can we have an array of instances for a custom module? For example: we can have input [15:0] a; - ... create 16 instances of the DFF module. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Arithmetic shift acts as a logical shift, regardless of the signed variable

I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's ... what I might be missing here? Thanks! See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - ADDRESS WIDTH from RAM DEPTH

I am implementing a configurable DPRAM where RAM DEPTH is the parameter. How to determine ADDRESS WIDTH from RAM ... 2) function in Verilog? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Error "procedural assignment to a non-register result is not permitted"

I'm getting the error [Synth 8-2576] procedural assignment to a non-register result is not permitted ["lpm_mult. ... * datab; end end endmodule See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Width independent functions

Is it possible to write a function that can detect the input data width automatically? For example, consider the ... code to be synthesizable. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - How to implement a (pseudo) hardware random number generator

How do you implement a hardware random number generator in an HDL (verilog)? What options need to be ... answers and updates are encouraged. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - how can I apply fixed fraction to the integer

I'd like to multiply to integer with modified fraction as following (Multiplication by power series summation with negative ... 3<<1024)>>10); See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - How much have xxx precision binary fixed point representation?

I am trying to measure how much have accuracy when I convert to binary fixed point representation way. first ... different on original value. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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