Recent questions tagged vhdl

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I'm trying to create a flexible array of constants. I want to use a 2D array which may sometimes be for ... even possible using a 2D array? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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vhdl - signed to std_logic_vector, slice results

I need to take the absolute value of a result and I am only interested in the most significant bits. This is ... I wrong? Thanks in advance c: See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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vhdl - Alternate way for port map in process?

As far as my understanding in vhdl, it is not possible to have port mappings to components within a process. and ... (the if/else conditions). See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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vhdl - Can custom types be used in port declaration?

I am preparing for an exam by going through some old ones. One of the questions is: Write the synthesizable ... inputs or outputs like that? See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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783 views

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vhdl - Verilog question mark (?) operator

I'm trying to translate a Verilog program into VHDL and have stumbled across a statement where a question mark ... in this context. Kind regards See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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540 views

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vhdl - Passing Generics to Record Port Types

I did recently start to use records for my port definitions, especially if I want to group signals that belong ... widths. Thanks a million, T See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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vhdl - Delta Cycles and Waveforms

Can anyone explain how delta cycles affect waveforms simulated by VHDL? I understand that it has to do with how ... 'm not exactly sure how. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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363 views

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vhdl - Delta Cycles and Waveforms

Can anyone explain how delta cycles affect waveforms simulated by VHDL? I understand that it has to do with how ... 'm not exactly sure how. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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473 views

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vhdl - Using array of std_logic_vector as a port type, with both ranges using a generic

Is it possible to create an entity with a port that is an array of std_logic_vectors, with both the size of ... without losing one's sanity)) See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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vhdl - When must a signal be inserted into the sensitivity list of a process

I am confused about when a signal declared in an architecture must be inserted into the sensitivity list of a ... in a process sensitivity list. See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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618 views

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vhdl - clk'event vs rising_edge()

I had always used this for detecting a rising edge: if (clk'event and clk='1') then but this can also ... these two? Any preferences? Thanks! See Question&Answers more detail:os...

asked Oct 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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370 views

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vhdl - Continuous assignment seemingly not working

I'm working on a FIR filter, specifically the delay line. x_delayed is initialized to all zeros. type slv32_array is ... ; end if; end process; See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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495 views

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vhdl - Error adding std_logic_vectors

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + ... natural numbers. Many thanks See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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388 views

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vhdl - How to count pressed keys on FPGA spartan board

I`m using FPGA Spartan 2 board and want to count the keys pressed from Keyboard this is my VHDL code : library ... a counter for pressed keys ? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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451 views

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vhdl - How does signal assignment work in a process?

I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In ... one is the correct way? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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