def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
     self.assertEqual(
         read_file(args_file).splitlines(),
         [
             "-compile",
             "-nocopyright",
             "-licqueue",
             "-nowarn DLCPTH",
             "-nowarn DLCVAR",
             "-v200x -extv200x",
             "-work work",
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
             "-quiet",
             '-nclibdirname ""',
             "-makelib lib_path",
             '"file.vhd"',
             "-endlib",
         ],
     )

 def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
     run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
     self.assertEqual(
         read_file(args_file).splitlines(),
         [
             "-compile",
             "-nocopyright",
             "-licqueue",
             "-nowarn UEXPSC",
             "-nowarn DLCPTH",
             "-nowarn DLCVAR",
             "-work work",
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-hdlvar "custom_hdlvar"',
             '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
             "-quiet",
             '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
             "-define defname=defval",
             '-nclibdirname ""',
             "-makelib lib",
             '"file.v"',
             "-endlib",
         ],
     )

 def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-v200x -extv200x',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
                       '-quiet',
                       '-nclibdirname ""',
                       '-makelib lib_path',
                       '"file.vhd"',
                       '-endlib'])

 def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn UEXPSC',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-hdlvar "custom_hdlvar"',
                       '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
                       '-quiet',
                       '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
                       '-define defname=defval',
                       '-nclibdirname ""',
                       '-makelib lib',
                       '"file.v"',
                       '-endlib'])

    def _preprocess(self, library_name, file_name, preprocessors):
        """
        Preprocess file_name within library_name using explicit preprocessors
        if preprocessors is None then use implicit globally defined processors
        """
        # @TODO dependency checking etc...

        if preprocessors is None:
            preprocessors = [self._location_preprocessor, self._check_preprocessor]
            preprocessors = [p for p in preprocessors if p is not None]
            preprocessors = self._external_preprocessors + preprocessors

        if len(preprocessors) == 0:
            return file_name

        code = ostools.read_file(file_name)
        for preprocessor in preprocessors:
            code = preprocessor.run(code, basename(file_name))

        pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))

        idx = 1
        while ostools.file_exists(pp_file_name):
            LOGGER.debug("Preprocessed file exists '%s', adding prefix", pp_file_name)
            pp_file_name = join(self._preprocessed_path,
                                library_name, "%i_%s" % (idx, basename(file_name)))
            idx += 1

        ostools.write_file(pp_file_name, code)
        return pp_file_name

    def _preprocess(self, library_name, file_name, preprocessors):
        # @TODO dependency checking etc...

        if preprocessors is None:
            preprocessors = [self._location_preprocessor, self._check_preprocessor]
            preprocessors = [p for p in preprocessors if not p is None]
            preprocessors = self._external_preprocessors + preprocessors

        if len(preprocessors) == 0:
            return file_name

        code = ostools.read_file(file_name)
        for p in preprocessors:
            code = p.run(code, basename(file_name))

        pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))

        idx = 1
        while ostools.file_exists(pp_file_name):
            logger.debug("Preprocessed file exists '%s', adding prefix" % pp_file_name)
            pp_file_name = join(self._preprocessed_path,
                                library_name, "%i_%s" % (idx, basename(file_name)))
            idx += 1

        ostools.write_file(pp_file_name, code)
        return pp_file_name

    def test_add_source_file_detects_illegal_vhdl_standard(self):
        write_file("file.vhd", "")

        project = Project()
        project.add_library("lib", "lib_path")
        self.assertRaises(ValueError, project.add_source_file, "file.vhd",
                          library_name="lib", file_type='vhdl', vhdl_standard='2007')

    def test_compile_project_vhdl_coverage(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  coverage="best",
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.vhd", "")
        project.add_source_file("file.vhd", "lib", file_type="vhdl")
        simif.compile_project(project, vhdl_standard="2008")
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vcom'),
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             '+cover=best',
                                             '-2008',
                                             '-work',
                                             'lib',
                                             'file.vhd'],
                                            simif._compile_output_consumer)  # pylint: disable=protected-access

def generate_codecs(input_package_design_unit, codec_package_name,  # pylint: disable=too-many-arguments
                    used_packages, output_file, debug):
    """This function generates codecs for the types in the input package and compile the result into
    codec_package_name. used_packages is a list specifying what to include into the result package
    other than the input package. A used package on the format 'lib.pkg' will result in a library and
    a use statement. A used package on the format 'pkg' is assumed to be located in work. output_file
    is where the resulting codec package is written. The debug codecs are generated when debug is set True."""

    # The design unit doesn't contain the package so it must be found first in the source file. This file
    # may contain other packages
    code = read_file(input_package_design_unit.source_file.name)
    package = CodecVHDLPackage.find_named_package(code, input_package_design_unit.name)
    if package is None:
        raise KeyError(input_package_design_unit.name)

    # Get all function declarations and definitions derived from the package type definitions
    declarations, definitions = package.generate_codecs_and_support_functions(debug)

    # Create extra use clauses
    use_clauses = ''
    libraries = []
    for used_package in used_packages if used_packages is not None else []:
        if '.' in used_package:
            if used_package.split('.')[0] not in libraries:
                libraries.append(used_package.split('.')[0])
                use_clauses += 'use %s.all;\n' % used_package
            else:
                use_clauses += 'use work.%s.all;\n' % used_package
    if len(libraries) != 0:
        use_clauses = 'library ' + ';\nlibrary '.join(libraries) + ';\n' + use_clauses

    # Assemble everything and write to output file
    codec_package_template = Template("""\
library vunit_lib;
use vunit_lib.string_ops.all;
context vunit_lib.com_context;

use std.textio.all;

use work.$package_name.all;

$use_clauses
package $codec_package_name is
$declarations
end package $codec_package_name;

package body $codec_package_name is
$definitions
end package body $codec_package_name;

""")

    codec_package = codec_package_template.substitute(
        declarations=declarations,
        definitions=definitions,
        package_name=package.identifier,
        codec_package_name=codec_package_name,
        use_clauses=use_clauses)

    write_file(output_file, codec_package)

    def test_compile_project_verilog_coverage(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  coverage="best",
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.v", "")
        project.add_source_file("file.v", "lib", file_type="verilog")
        simif.compile_project(project)
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vlog'),
                                             '-sv',
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             '+cover=best',
                                             '-work',
                                             'lib',
                                             'file.v',
                                             '-L', 'lib'])

 def _create_modelsim_ini(self):
     """
     Create the modelsim.ini file if it does not exist
     """
     if file_exists(self._modelsim_ini):
         return
     write_file(self._modelsim_ini, read_file(join(self._prefix, "..", "modelsim.ini")))

    def test_compile_project_vhdl_extra_flags(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.vhd", "")
        source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
        source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
        simif.compile_project(project)
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vcom'),
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             'custom',
                                             'flags',
                                             '-2008',
                                             '-work',
                                             'lib',
                                             'file.vhd'])

    def test_finds_verilog_include_dependencies(self):
        def create_project():
            """
            Create the test project
            """
            self.project = Project()
            self.project.add_library("lib", "lib_path")
            self.add_source_file("lib", "module.sv", """\
`include "include.svh"
""")

        write_file("include.svh", """\
module name;
endmodule
""")
        create_project()
        self.assert_should_recompile(["module.sv"])

        for src_file in self.project.get_files_in_compile_order():
            self.update(src_file.name)
        create_project()
        self.assert_should_recompile([])

        write_file("include.svh", """\
module other_name;
endmodule
""")
        create_project()
        self.assert_should_recompile(["module.sv"])

    def _create_cdslib(self):
        """
        Create the cds.lib file in the output directory if it does not exist
        """
        cds_root_virtuoso = self.find_cds_root_virtuoso()

        if cds_root_virtuoso is None:
            contents = """\
## cds.lib: Defines the locations of compiled libraries.
softinclude {0}/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define work "{1}/libraries/work"
""".format(self._cds_root_irun, self._output_path)
        else:
            contents = """\
## cds.lib: Defines the locations of compiled libraries.
softinclude {0}/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
define basic "{1}/tools/dfII/etc/cdslib/basic"
define work "{2}/libraries/work"
""".format(self._cds_root_irun, cds_root_virtuoso, self._output_path)

        write_file(self._cdslib, contents)

 def compile_vhdl_file_command(self, source_file):
     """
     Returns command to compile a VHDL file
     """
     cmd = join(self._prefix, 'irun')
     args = []
     args += ['-compile']
     args += ['-nocopyright']
     args += ['-licqueue']
     args += ['-nowarn DLCPTH']  # "cds.lib Invalid path"
     args += ['-nowarn DLCVAR']  # "cds.lib Invalid environment variable ''."
     args += ['%s' % self._vhdl_std_opt(source_file.get_vhdl_standard())]
     args += ['-work work']
     args += ['-cdslib "%s"' % self._cdslib]
     args += self._hdlvar_args()
     args += ['-log "%s"' % join(self._output_path, "irun_compile_vhdl_file_%s.log" % source_file.library.name)]
     if not self._log_level == "debug":
         args += ['-quiet']
     else:
         args += ['-messages']
         args += ['-libverbose']
     args += source_file.compile_options.get('incisive.irun_vhdl_flags', [])
     args += ['-nclibdirname "%s"' % dirname(source_file.library.directory)]
     args += ['-makelib %s' % source_file.library.directory]
     args += ['"%s"' % source_file.name]
     args += ['-endlib']
     argsfile = join(self._output_path, "irun_compile_vhdl_file_%s.args" % source_file.library.name)
     write_file(argsfile, "\n".join(args))
     return [cmd, '-f', argsfile]

 def compile_verilog_file_command(self, source_file):
     """
     Returns commands to compile a Verilog file
     """
     cmd = join(self._prefix, 'vlogan')
     args = []
     args += ['-compile']
     args += ['-debug_all']
     args += ['-sverilog'] # SystemVerilog
     args += ['+v2k'] # Verilog 2001
     args += ['-work %s' % source_file.library.name]
     args += source_file.compile_options.get('vcs_verilog_flags', [])
     args += ['-l %s/vcs_compile_verilog_file_%s.log' % (self._output_path, source_file.library.name)]
     if not self._log_level == "debug":
         args += ['-q']
         args += ['-nc']
     else:
         args += ['-V']
         args += ['-notice']
         args += ['+libverbose']
     for include_dir in source_file.include_dirs:
         args += ['+incdir+%s' % include_dir]
     for key, value in source_file.defines.items():
         args += ['+define+%s=%s' % (key, value.replace('"','\\"'))]
     args += ['%s' % source_file.name]
     argsfile = "%s/vcs_compile_verilog_file_%s.args" % (self._output_path, source_file.library.name)
     write_file(argsfile, "\n".join(args))
     return [cmd, '-full64', '-f', argsfile]

    def test_compile_project_verilog_define(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.v", "")
        project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
        simif.compile_project(project, vhdl_standard="2008")
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vlog'),
                                             '-sv',
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             '-work',
                                             'lib',
                                             'file.v',
                                             '-L', 'lib',
                                             '+define+defname=defval'],
                                            simif._compile_output_consumer)  # pylint: disable=protected-access

 def update(self, source_file):
     """
     Mark that source_file has been recompiled, triggers a re-write of the hash file
     to update the timestamp
     """
     new_content_hash = source_file.content_hash
     ostools.write_file(self._hash_file_name_of(source_file), new_content_hash)
     LOGGER.debug('Wrote %s content_hash=%s', source_file.name, new_content_hash)

 def write(self, file_name):
     """
     Write cds file to file named 'file_name'
     """
     contents = "\n".join(self._other_lines +
                          ['define %s "%s"' % item
                           for item in sorted(self.items())]) + "\n"
     write_file(file_name, contents)

    def test_compile_project_verilog_error(self):
        simif = GHDLInterface(prefix="prefix")
        write_file("file.v", "")

        project = Project()
        project.add_library("lib", "lib_path")
        project.add_source_file("file.v", "lib", file_type="verilog")
        self.assertRaises(CompileError, simif.compile_project, project, vhdl_standard="2008")