本文整理汇总了C++中snd_soc_codec_get_drvdata函数的典型用法代码示例。如果您正苦于以下问题：C++ snd_soc_codec_get_drvdata函数的具体用法？C++ snd_soc_codec_get_drvdata怎么用？C++ snd_soc_codec_get_drvdata使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了snd_soc_codec_get_drvdata函数的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: arizona_set_sysclk
int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
int source, unsigned int freq, int dir)
{
struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
struct arizona *arizona = priv->arizona;
char *name;
unsigned int reg;
unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
unsigned int *clk;
switch (clk_id) {
case ARIZONA_CLK_SYSCLK:
name = "SYSCLK";
reg = ARIZONA_SYSTEM_CLOCK_1;
clk = &priv->sysclk;
mask |= ARIZONA_SYSCLK_FRAC;
break;
case ARIZONA_CLK_ASYNCCLK:
name = "ASYNCCLK";
reg = ARIZONA_ASYNC_CLOCK_1;
clk = &priv->asyncclk;
break;
case ARIZONA_CLK_OPCLK:
case ARIZONA_CLK_ASYNC_OPCLK:
return arizona_set_opclk(codec, clk_id, freq);
default:
return -EINVAL;
}
switch (freq) {
case 5644800:
case 6144000:
break;
case 11289600:
case 12288000:
val |= 1 << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 22579200:
case 24576000:
val |= 2 << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 45158400:
case 49152000:
val |= 3 << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 67737600:
case 73728000:
val |= 4 << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 90316800:
case 98304000:
val |= 5 << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 135475200:
case 147456000:
val |= 6 << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
default:
return -EINVAL;
}
*clk = freq;
if (freq % 6144000)
val |= ARIZONA_SYSCLK_FRAC;
dev_dbg(arizona->dev, "%s set to %uHz\n", name, freq);
//printk("---------------------- here we are %u,%u,%s,%i,%i\n",val,freq,name,reg,mask);
return regmap_update_bits(arizona->regmap, reg, mask, val);
}
开发者ID:AirShark，项目名称:android_kernel_lenovo_redhookbay，代码行数:72，代码来源:arizona.c
示例2: sta32x_hw_params
/**
* sta32x_hw_params - program the STA32X with the given hardware parameters.
* @substream: the audio stream
* @params: the hardware parameters to set
* @dai: the SOC DAI (ignored)
*
* This function programs the hardware with the values provided.
* Specifically, the sample rate and the data format.
*/
static int sta32x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
unsigned int rate;
int i, mcs = -1, ir = -1;
u8 confa, confb;
rate = params_rate(params);
pr_debug("rate: %u\n", rate);
for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++)
if (interpolation_ratios[i].fs == rate) {
ir = interpolation_ratios[i].ir;
break;
}
if (ir < 0)
return -EINVAL;
for (i = 0; mclk_ratios[ir][i].ratio; i++)
if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) {
mcs = mclk_ratios[ir][i].mcs;
break;
}
if (mcs < 0)
return -EINVAL;
confa = snd_soc_read(codec, STA32X_CONFA);
confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK);
confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT);
confb = snd_soc_read(codec, STA32X_CONFB);
confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB);
switch (params_width(params)) {
case 24:
pr_debug("24bit\n");
/* fall through */
case 32:
pr_debug("24bit or 32bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x1;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0x2;
break;
}
break;
case 20:
pr_debug("20bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x4;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x5;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0x6;
break;
}
break;
case 18:
pr_debug("18bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x8;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x9;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0xa;
break;
}
break;
case 16:
pr_debug("16bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0xd;
break;
//.........这里部分代码省略.........
开发者ID:383530895，项目名称:linux，代码行数:101，代码来源:sta32x.c
示例3: aic31xx_setup_pll
static int aic31xx_setup_pll(struct snd_soc_codec *codec,
struct snd_pcm_hw_params *params)
{
struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
int bclk_score = snd_soc_params_to_frame_size(params);
int mclk_p = aic31xx->sysclk / aic31xx->p_div;
int bclk_n = 0;
int match = -1;
int i;
/* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
snd_soc_update_bits(codec, AIC31XX_CLKMUX,
AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
snd_soc_update_bits(codec, AIC31XX_IFACE2,
AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
if (aic31xx_divs[i].rate == params_rate(params) &&
aic31xx_divs[i].mclk_p == mclk_p) {
int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
snd_soc_params_to_frame_size(params);
int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
snd_soc_params_to_frame_size(params);
if (s < bclk_score && bn > 0) {
match = i;
bclk_n = bn;
bclk_score = s;
}
}
}
if (match == -1) {
dev_err(codec->dev,
"%s: Sample rate (%u) and format not supported\n",
__func__, params_rate(params));
/* See bellow for details how fix this. */
return -EINVAL;
}
if (bclk_score != 0) {
dev_warn(codec->dev, "Can not produce exact bitclock");
/* This is fine if using dsp format, but if using i2s
there may be trouble. To fix the issue edit the
aic31xx_divs table for your mclk and sample
rate. Details can be found from:
http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
Section: 5.6 CLOCK Generation and PLL
*/
}
i = match;
/* PLL configuration */
snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
(aic31xx->p_div << 4) | 0x01);
snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
snd_soc_write(codec, AIC31XX_PLLDMSB,
aic31xx_divs[i].pll_d >> 8);
snd_soc_write(codec, AIC31XX_PLLDLSB,
aic31xx_divs[i].pll_d & 0xff);
/* DAC dividers configuration */
snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK,
aic31xx_divs[i].ndac);
snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK,
aic31xx_divs[i].mdac);
snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
/* ADC dividers configuration. Write reset value 1 if not used. */
snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK,
aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK,
aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
/* Bit clock divider configuration. */
snd_soc_update_bits(codec, AIC31XX_BCLKN,
AIC31XX_PLL_MASK, bclk_n);
aic31xx->rate_div_line = i;
dev_dbg(codec->dev,
"pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
aic31xx->p_div, aic31xx_divs[i].dosr,
aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
aic31xx_divs[i].madc, bclk_n);
return 0;
}
开发者ID:383530895，项目名称:linux，代码行数:93，代码来源:tlv320aic31xx.c
示例4: adau1977_set_tdm_slot
static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int width)
{
struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
unsigned int ctrl0, ctrl1, drv;
unsigned int slot[4];
unsigned int i;
int ret;
if (slots == 0) {
/* 0 = No fixed slot width */
adau1977->slot_width = 0;
adau1977->max_master_fs = 192000;
return regmap_update_bits(adau1977->regmap,
ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
ADAU1977_SAI_CTRL0_SAI_I2S);
}
if (rx_mask == 0 || tx_mask != 0)
return -EINVAL;
drv = 0;
for (i = 0; i < 4; i++) {
slot[i] = __ffs(rx_mask);
drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
rx_mask &= ~(1 << slot[i]);
if (slot[i] >= slots)
return -EINVAL;
if (rx_mask == 0)
break;
}
if (rx_mask != 0)
return -EINVAL;
switch (width) {
case 16:
ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
break;
case 24:
/* We can only generate 16 bit or 32 bit wide slots */
if (adau1977->master)
return -EINVAL;
ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
break;
case 32:
ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
break;
default:
return -EINVAL;
}
switch (slots) {
case 2:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
break;
case 4:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
break;
case 8:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
break;
case 16:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
ADAU1977_SAI_OVERTEMP_DRV_C(0) |
ADAU1977_SAI_OVERTEMP_DRV_C(1) |
ADAU1977_SAI_OVERTEMP_DRV_C(2) |
ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
if (ret)
return ret;
ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
(slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
(slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
if (ret)
return ret;
ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
(slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
(slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
if (ret)
return ret;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
if (ret)
return ret;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
if (ret)
return ret;
adau1977->slot_width = width;
//.........这里部分代码省略.........
开发者ID:AshishNamdev，项目名称:linux，代码行数:101，代码来源:adau1977.c
示例5: cs4271_hw_params
static int cs4271_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
int i, ret;
unsigned int ratio, val;
if (cs4271->enable_soft_reset) {
/*
* Put the codec in soft reset and back again in case it's not
* currently streaming data. This way of bringing the codec in
* sync to the current clocks is not explicitly documented in
* the data sheet, but it seems to work fine, and in contrast
* to a read hardware reset, we don't have to sync back all
* registers every time.
*/
if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
!dai->capture_active) ||
(substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
!dai->playback_active)) {
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN,
CS4271_MODE2_PDN);
if (ret < 0)
return ret;
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN, 0);
if (ret < 0)
return ret;
}
}
cs4271->rate = params_rate(params);
/* Configure DAC */
if (cs4271->rate < 50000)
val = CS4271_MODE1_MODE_1X;
else if (cs4271->rate < 100000)
val = CS4271_MODE1_MODE_2X;
else
val = CS4271_MODE1_MODE_4X;
ratio = cs4271->mclk / cs4271->rate;
for (i = 0; i < CS4171_NR_RATIOS; i++)
if ((cs4271_clk_tab[i].master == cs4271->master) &&
(cs4271_clk_tab[i].speed_mode == val) &&
(cs4271_clk_tab[i].ratio == ratio))
break;
if (i == CS4171_NR_RATIOS) {
dev_err(codec->dev, "Invalid sample rate\n");
return -EINVAL;
}
val |= cs4271_clk_tab[i].ratio_mask;
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
if (ret < 0)
return ret;
return cs4271_set_deemph(codec);
}
开发者ID:020gzh，项目名称:linux，代码行数:67，代码来源:cs4271.c
示例6: wm0010_firmware_load
static int wm0010_firmware_load(const char *name, struct snd_soc_codec *codec)
{
struct spi_device *spi = to_spi_device(codec->dev);
struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
struct list_head xfer_list;
struct wm0010_boot_xfer *xfer;
int ret;
struct completion done;
const struct firmware *fw;
const struct dfw_binrec *rec;
const struct dfw_inforec *inforec;
u64 *img;
u8 *out, dsp;
u32 len, offset;
INIT_LIST_HEAD(&xfer_list);
ret = request_firmware(&fw, name, codec->dev);
if (ret != 0) {
dev_err(codec->dev, "Failed to request application(%s): %d\n",
name, ret);
return ret;
}
rec = (const struct dfw_binrec *)fw->data;
inforec = (const struct dfw_inforec *)rec->data;
offset = 0;
dsp = inforec->dsp_target;
wm0010->boot_failed = false;
if (WARN_ON(!list_empty(&xfer_list)))
return -EINVAL;
init_completion(&done);
/* First record should be INFO */
if (rec->command != DFW_CMD_INFO) {
dev_err(codec->dev, "First record not INFO\r\n");
ret = -EINVAL;
goto abort;
}
if (inforec->info_version != INFO_VERSION) {
dev_err(codec->dev,
"Unsupported version (%02d) of INFO record\r\n",
inforec->info_version);
ret = -EINVAL;
goto abort;
}
dev_dbg(codec->dev, "Version v%02d INFO record found\r\n",
inforec->info_version);
/* Check it's a DSP file */
if (dsp != DEVICE_ID_WM0010) {
dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
ret = -EINVAL;
goto abort;
}
/* Skip the info record as we don't need to send it */
offset += ((rec->length) + 8);
rec = (void *)&rec->data[rec->length];
while (offset < fw->size) {
dev_dbg(codec->dev,
"Packet: command %d, data length = 0x%x\r\n",
rec->command, rec->length);
len = rec->length + 8;
xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
if (!xfer) {
ret = -ENOMEM;
goto abort;
}
xfer->codec = codec;
list_add_tail(&xfer->list, &xfer_list);
out = kzalloc(len, GFP_KERNEL | GFP_DMA);
if (!out) {
ret = -ENOMEM;
goto abort1;
}
xfer->t.rx_buf = out;
img = kzalloc(len, GFP_KERNEL | GFP_DMA);
if (!img) {
ret = -ENOMEM;
goto abort1;
}
xfer->t.tx_buf = img;
byte_swap_64((u64 *)&rec->command, img, len);
spi_message_init(&xfer->m);
xfer->m.complete = wm0010_boot_xfer_complete;
xfer->m.context = xfer;
xfer->t.len = len;
xfer->t.bits_per_word = 8;
if (!wm0010->pll_running) {
//.........这里部分代码省略.........
开发者ID:mikuhatsune001，项目名称:linux2.6.32，代码行数:101，代码来源:wm0010.c
示例7: wm0010_boot
static int wm0010_boot(struct snd_soc_codec *codec)
{
struct spi_device *spi = to_spi_device(codec->dev);
struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
unsigned long flags;
int ret;
const struct firmware *fw;
struct spi_message m;
struct spi_transfer t;
struct dfw_pllrec pll_rec;
u32 *p, len;
u64 *img_swap;
u8 *out;
int i;
spin_lock_irqsave(&wm0010->irq_lock, flags);
if (wm0010->state != WM0010_POWER_OFF)
dev_warn(wm0010->dev, "DSP already powered up!\n");
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
if (wm0010->sysclk > 26000000) {
dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
ret = -ECANCELED;
goto err;
}
mutex_lock(&wm0010->lock);
wm0010->pll_running = false;
dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
wm0010->core_supplies);
if (ret != 0) {
dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
ret);
mutex_unlock(&wm0010->lock);
goto err;
}
ret = regulator_enable(wm0010->dbvdd);
if (ret != 0) {
dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
goto err_core;
}
/* Release reset */
gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_OUT_OF_RESET;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
/* First the bootloader */
ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
if (ret != 0) {
dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
ret);
goto abort;
}
if (!wait_for_completion_timeout(&wm0010->boot_completion,
msecs_to_jiffies(20)))
dev_err(codec->dev, "Failed to get interrupt from DSP\n");
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_BOOTROM;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
ret = wm0010_stage2_load(codec);
if (ret)
goto abort;
if (!wait_for_completion_timeout(&wm0010->boot_completion,
msecs_to_jiffies(20)))
dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_STAGE2;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
/* Only initialise PLL if max_spi_freq initialised */
if (wm0010->max_spi_freq) {
/* Initialise a PLL record */
memset(&pll_rec, 0, sizeof(pll_rec));
pll_rec.command = DFW_CMD_PLL;
pll_rec.length = (sizeof(pll_rec) - 8);
/* On wm0010 only the CLKCTRL1 value is used */
pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
ret = -ENOMEM;
len = pll_rec.length + 8;
out = kzalloc(len, GFP_KERNEL | GFP_DMA);
if (!out) {
dev_err(codec->dev,
"Failed to allocate RX buffer\n");
goto abort;
}
//.........这里部分代码省略.........
开发者ID:mikuhatsune001，项目名称:linux2.6.32，代码行数:101，代码来源:wm0010.c
示例8: wm8955_configure_clocking
static int wm8955_configure_clocking(struct snd_soc_codec *codec)
{
struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
int i, ret, val;
int clocking = 0;
int srate = 0;
int sr = -1;
struct pll_factors pll;
/* If we're not running a sample rate currently just pick one */
if (wm8955->fs == 0)
wm8955->fs = 8000;
/* Can we generate an exact output? */
for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
if (wm8955->fs != clock_cfgs[i].fs)
continue;
sr = i;
if (wm8955->mclk_rate == clock_cfgs[i].mclk)
break;
}
/* We should never get here with an unsupported sample rate */
if (sr == -1) {
dev_err(codec->dev, "Sample rate %dHz unsupported\n",
wm8955->fs);
WARN_ON(sr == -1);
return -EINVAL;
}
if (i == ARRAY_SIZE(clock_cfgs)) {
/* If we can't generate the right clock from MCLK then
* we should configure the PLL to supply us with an
* appropriate clock.
*/
clocking |= WM8955_MCLKSEL;
/* Use the last divider configuration we saw for the
* sample rate. */
ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
clock_cfgs[sr].mclk, &pll);
if (ret != 0) {
dev_err(codec->dev,
"Unable to generate %dHz from %dHz MCLK\n",
wm8955->fs, wm8955->mclk_rate);
return -EINVAL;
}
snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
WM8955_N_MASK | WM8955_K_21_18_MASK,
(pll.n << WM8955_N_SHIFT) |
pll.k >> 18);
snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
WM8955_K_17_9_MASK,
(pll.k >> 9) & WM8955_K_17_9_MASK);
snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
WM8955_K_8_0_MASK,
pll.k & WM8955_K_8_0_MASK);
if (pll.k)
snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
WM8955_KEN, WM8955_KEN);
else
snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
WM8955_KEN, 0);
if (pll.outdiv)
val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
else
val = WM8955_PLL_RB;
/* Now start the PLL running */
snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
WM8955_PLLEN, WM8955_PLLEN);
}
开发者ID:openube，项目名称:android_kernel_sony_c2305，代码行数:77，代码来源:wm8955.c
示例9: rt5616_set_dai_pll
static int rt5616_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5616->pll_src && freq_in == rt5616->pll_in &&
freq_out == rt5616->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(codec->dev, "PLL disabled\n");
rt5616->pll_in = 0;
rt5616->pll_out = 0;
snd_soc_update_bits(codec, RT5616_GLB_CLK,
RT5616_SCLK_SRC_MASK,
RT5616_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5616_PLL1_S_MCLK:
snd_soc_update_bits(codec, RT5616_GLB_CLK,
RT5616_PLL1_SRC_MASK,
RT5616_PLL1_SRC_MCLK);
break;
case RT5616_PLL1_S_BCLK1:
case RT5616_PLL1_S_BCLK2:
snd_soc_update_bits(codec, RT5616_GLB_CLK,
RT5616_PLL1_SRC_MASK,
RT5616_PLL1_SRC_BCLK1);
break;
default:
dev_err(codec->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
return ret;
}
dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_write(codec, RT5616_PLL_CTRL1,
pll_code.n_code << RT5616_PLL_N_SFT | pll_code.k_code);
snd_soc_write(codec, RT5616_PLL_CTRL2,
(pll_code.m_bp ? 0 : pll_code.m_code) <<
RT5616_PLL_M_SFT |
pll_code.m_bp << RT5616_PLL_M_BP_SFT);
rt5616->pll_in = freq_in;
rt5616->pll_out = freq_out;
rt5616->pll_src = source;
return 0;
}
开发者ID:AshishNamdev，项目名称:linux，代码行数:63，代码来源:rt5616.c
示例10: max98925_probe
static int max98925_probe(struct snd_soc_codec *codec)
{
struct max98925_priv *max98925 = snd_soc_codec_get_drvdata(codec);
struct max98925_cdata *cdata;
int ret = 0;
int reg = 0;
dev_info(codec->dev, "MONO - built on %s at %s\n",
__DATE__,
__TIME__);
dev_info(codec->dev, "build number %s\n", MAX98925_REVISION);
max98925->codec = codec;
codec->control_data = max98925->regmap;
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
if (ret != 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
return ret;
}
max98925->sysclk = 12288000;
max98925->volume = 0x07;
cdata = &max98925->dai[0];
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
reg = 0;
ret = regmap_read(max98925->regmap, MAX98925_R0FF_VERSION, ®);
if ((ret < 0) || ((reg != MAX98925_VERSION)
&& (reg != MAX98925_VERSION1)
&& (reg != MAX98925_VERSION2)
&& (reg != MAX98925_VERSION3))) {
dev_err(codec->dev,
"device initialization error (%d 0x%02X)\n",
ret,
reg);
goto err_access;
}
dev_info(codec->dev, "device version 0x%02X\n", reg);
regmap_write(max98925->regmap, MAX98925_R038_GLOBAL_ENABLE, 0x00);
/* It's not the default but we need to set DAI_DLY */
regmap_write(max98925->regmap, MAX98925_R020_FORMAT,
MAX98925_DAI_DLY_MASK);
regmap_write(max98925->regmap, MAX98925_R021_TDM_SLOT_SELECT, 0xC8);
regmap_write(max98925->regmap, MAX98925_R027_DOUT_HIZ_CFG1, 0xFF);
regmap_write(max98925->regmap, MAX98925_R028_DOUT_HIZ_CFG2, 0xFF);
regmap_write(max98925->regmap, MAX98925_R029_DOUT_HIZ_CFG3, 0xFF);
regmap_write(max98925->regmap, MAX98925_R02A_DOUT_HIZ_CFG4, 0xF0);
regmap_write(max98925->regmap, MAX98925_R02C_FILTERS, 0xD8);
regmap_write(max98925->regmap, MAX98925_R034_ALC_CONFIGURATION, 0x12);
/*****************************************************************/
/* Set boost output to minimum until DSM is implemented */
regmap_write(max98925->regmap, MAX98925_R037_CONFIGURATION, 0xF0);
/*****************************************************************/
/* Disable ALC muting */
regmap_write(max98925->regmap, MAX98925_R03A_BOOST_LIMITER, 0xF8);
regmap_update_bits(max98925->regmap,
MAX98925_R02D_GAIN, MAX98925_DAC_IN_SEL_MASK,
MAX98925_DAC_IN_SEL_DIV2_SUMMED_DAI);
max98925_handle_pdata(codec);
max98925_add_widgets(codec);
err_access:
msg_maxim("%s: exit %d\n", __func__, ret);
return ret;
}
开发者ID:bju2000，项目名称:kernel_lge_msm8994，代码行数:79，代码来源:max98925.c
示例11: wm8400_codec_reset
static void wm8400_codec_reset(struct snd_soc_codec *codec)
{
struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
wm8400_reset_codec_reg_cache(wm8400->wm8400);
}
开发者ID:romanbb，项目名称:android_kernel_lge_d851，代码行数:6，代码来源:wm8400.c
示例12: max98925_dai_set_fmt
static int max98925_dai_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct max98925_priv *max98925 = snd_soc_codec_get_drvdata(codec);
struct max98925_cdata *cdata;
unsigned int invert = 0;
msg_maxim("%s: fmt 0x%08X\n", __func__, fmt);
cdata = &max98925->dai[0];
cdata->fmt = fmt;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
max98925_set_slave(max98925);
break;
case SND_SOC_DAIFMT_CBM_CFM:
max98925_set_master(max98925);
break;
case SND_SOC_DAIFMT_CBS_CFM:
case SND_SOC_DAIFMT_CBM_CFS:
default:
dev_err(codec->dev, "DAI clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
msg_maxim("%s: set SND_SOC_DAIFMT_I2S\n", __func__);
break;
case SND_SOC_DAIFMT_LEFT_J:
msg_maxim("%s: set SND_SOC_DAIFMT_LEFT_J\n", __func__);
break;
case SND_SOC_DAIFMT_DSP_A:
msg_maxim("%s: set SND_SOC_DAIFMT_DSP_A\n", __func__);
default:
dev_err(codec->dev, "DAI format unsupported, fmt:0x%x", fmt);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
invert = MAX98925_DAI_WCI_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98925_DAI_BCI_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
invert = MAX98925_DAI_BCI_MASK | MAX98925_DAI_WCI_MASK;
break;
default:
dev_err(codec->dev, "DAI invert mode unsupported");
return -EINVAL;
}
regmap_update_bits(max98925->regmap, MAX98925_R020_FORMAT,
MAX98925_DAI_BCI_MASK | MAX98925_DAI_BCI_MASK, invert);
return 0;
}
开发者ID:bju2000，项目名称:kernel_lge_msm8994，代码行数:64，代码来源:max98925.c
示例13: tabla_codec_enable_micbias2
void tabla_codec_enable_micbias2(struct snd_soc_codec *codec)
{
#if 1
pr_info("%s\n", __func__ );
snd_soc_write(codec, TABLA_A_MICB_CFILT_2_CTL, 0x80);
snd_soc_write(codec, TABLA_A_MICB_2_CTL, 0xb6);
snd_soc_write(codec, TABLA_A_LDO_H_MODE_1, 0xCD);
snd_soc_write(codec, TABLA_A_MICB_CFILT_2_VAL, 0x68);
#else
#if 0
snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x0F, 0x0D);
snd_soc_update_bits(codec, TABLA_A_TX_COM_BIAS, 0xE0, 0xE0);
snd_soc_write(codec, TABLA_A_MICB_CFILT_2_VAL, 0x68);
snd_soc_update_bits(codec, TABLA_A_MICB_2_CTL, 0x60, 0x20);
snd_soc_update_bits(codec, TABLA_A_MICB_2_CTL, 0x0E, 0x0A);
snd_soc_update_bits(codec, TABLA_A_MICB_CFILT_2_CTL, 0x80, 0x80);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
#else
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
// short bias_value;
tabla->mbhc_polling_active = true;
snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1, 0x05, 0x01);
snd_soc_update_bits(codec, TABLA_A_TX_COM_BIAS, 0xE0, 0xE0);
snd_soc_write(codec, TABLA_A_MICB_CFILT_2_CTL, 0x00);
snd_soc_update_bits(codec, TABLA_A_MICB_2_CTL, 0x1F, 0x16);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x80, 0x80);
snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x1F, 0x1C);
snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_TEST_CTL, 0x40, 0x40);
snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x80, 0x00);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x00);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x6, 0x6);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
snd_soc_update_bits(codec, TABLA_A_MICB_2_MBHC, 0x10, 0x10);
snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x01);
//tabla_codec_calibrate_hs_polling(codec);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B10_CTL, 0xFF);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B9_CTL, 0x00);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL, 0x08);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL, 0xEE);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL, 0xFC);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL, 0xCE);
snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B1_CTL, 3);
snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B2_CTL, 9);
snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B3_CTL, 30);
snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B6_CTL, 120);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_TIMER_B1_CTL, 0x78, 0x58);
snd_soc_write(codec, TABLA_A_CDC_MBHC_B2_CTL, 11);
//bias_value = tabla_codec_measure_micbias_voltage(codec, 0);
snd_soc_write(codec, TABLA_A_MICB_CFILT_2_CTL, 0x40);
snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_REMOVAL);
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_POTENTIAL);
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_RELEASE);
//tabla_codec_enable_bandgap(codec, TABLA_BANDGAP_OFF);
snd_soc_write(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x00);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x0);
#endif
#endif
}
开发者ID:GameTheory-，项目名称:android_kernel_lge_l1v，代码行数:86，代码来源:fsa8008.c
示例14: arizona_hw_params
static int arizona_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
unsigned int val;
int base = dai->driver->base;
const int *rates;
int i, ret, bclk_target;
int bclk, lrclk, wl, frame, sr_val;
//printk("Arizona: hw params start\n");
if (params_rate(params) % 8000)
rates = &arizona_44k1_bclk_rates[0];
else
rates = &arizona_48k_bclk_rates[0];
/* Force BCLK to stereo for I2S */
bclk_target = snd_soc_params_to_bclk(params);
val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
if (val & ARIZONA_AIF1_FMT_MASK && params_channels(params) == 1) {
arizona_aif_err(dai, "Forcing stereo mode\n");
bclk_target *= 2;
}
for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
if (rates[i] >= bclk_target &&
rates[i] % params_rate(params) == 0) {
bclk = i;
break;
}
}
if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
params_rate(params));
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
if (arizona_sr_vals[i] == params_rate(params))
break;
if (i == ARRAY_SIZE(arizona_sr_vals)) {
arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
params_rate(params));
return -EINVAL;
}
sr_val = i;
lrclk = rates[bclk] / params_rate(params);
arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
rates[bclk], rates[bclk] / lrclk);
wl = snd_pcm_format_width(params_format(params));
frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
/*
* We will need to be more flexible than this in future,
* currently we use a single sample rate for SYSCLK.
*/
switch (dai_priv->clk) {
case ARIZONA_CLK_SYSCLK:
/* SR2 is forced to 8kHz */
if (params_rate(params) != 8000) {
snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
ARIZONA_AIF1_RATE_MASK, 0);
} else {
snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_2,
ARIZONA_SAMPLE_RATE_2_MASK, sr_val);
snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
ARIZONA_AIF1_RATE_MASK, 1);
}
break;
case ARIZONA_CLK_ASYNCCLK:
snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
ARIZONA_AIF1_RATE_MASK, 8);
break;
default:
arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
return -EINVAL;
}
snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE,
ARIZONA_AIF1TX_BCPF_MASK, lrclk);
snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE,
ARIZONA_AIF1RX_BCPF_MASK, lrclk);
snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1,
ARIZONA_AIF1TX_WL_MASK |
ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2,
ARIZONA_AIF1RX_WL_MASK |
ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
//.........这里部分代码省略.........
开发者ID:AirShark，项目名称:android_kernel_lenovo_redhookbay，代码行数:101，代码来源:arizona.c
示例15: twl6040_set_dai_sysclk
static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
u8 hppllctl, lppllctl;
hppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_HPPLLCTL);
lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
switch (clk_id) {
case TWL6040_SYSCLK_SEL_LPPLL:
switch (freq) {
case 32768:
/* headset dac and driver must be in low-power mode */
headset_power_mode(codec, 0);
/* clk32k input requires low-power pll */
lppllctl |= TWL6040_LPLLENA;
twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
mdelay(5);
lppllctl &= ~TWL6040_HPLLSEL;
twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
hppllctl &= ~TWL6040_HPLLENA;
twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl);
break;
default:
dev_err(codec->dev, "unknown mclk freq %d\n", freq);
return -EINVAL;
}
/* lppll divider */
switch (priv->sysclk) {
case 17640000:
lppllctl |= TWL6040_LPLLFIN;
break;
case 19200000:
lppllctl &= ~TWL6040_LPLLFIN;
break;
default:
/* sysclk not yet configured */
lppllctl &= ~TWL6040_LPLLFIN;
priv->sysclk = 19200000;
break;
}
twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
priv->pll = TWL6040_LPPLL_ID;
priv->sysclk_constraints = &lp_constraints;
break;
case TWL6040_SYSCLK_SEL_HPPLL:
hppllctl &= ~TWL6040_MCLK_MSK;
switch (freq) {
case 12000000:
/* mclk input, pll enabled */
hppllctl |= TWL6040_MCLK_12000KHZ |
TWL6040_HPLLSQRBP |
TWL6040_HPLLENA;
break;
case 19200000:
/* mclk input, pll disabled */
hppllctl |= TWL6040_MCLK_19200KHZ |
TWL6040_HPLLSQRENA |
TWL6040_HPLLBP;
break;
case 26000000:
/* mclk input, pll enabled */
hppllctl |= TWL6040_MCLK_26000KHZ |
TWL6040_HPLLSQRBP |
TWL6040_HPLLENA;
break;
case 38400000:
/* clk slicer, pll disabled */
hppllctl |= TWL6040_MCLK_38400KHZ |
TWL6040_HPLLSQRENA |
TWL6040_HPLLBP;
break;
default:
dev_err(codec->dev, "unknown mclk freq %d\n", freq);
return -EINVAL;
}
/* headset dac and driver must be in high-performance mode */
headset_power_mode(codec, 1);
twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl);
udelay(500);
lppllctl |= TWL6040_HPLLSEL;
twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
lppllctl &= ~TWL6040_LPLLENA;
twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
/* high-performance pll can provide only 19.2 MHz */
priv->pll = TWL6040_HPPLL_ID;
priv->sysclk = 19200000;
priv->sysclk_constraints = &hp_constraints;
break;
default:
//.........这里部分代码省略.........
开发者ID:3sOx，项目名称:asuswrt-merlin，代码行数:101，代码来源:twl6040.c
示例16: rt5616_set_bias_level
static int rt5616_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/*
* SND_SOC_BIAS_PREPARE is called while preparing for a
* transition to ON or away from ON. If current bias_level
* is SND_SOC_BIAS_ON, then it is preparing for a transition
* away from ON. Disable the clock in that case, otherwise
* enable it.
*/
if (IS_ERR(rt5616->mclk))
break;
if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
clk_disable_unprepare(rt5616->mclk);
} else {
ret = clk_prepare_enable(rt5616->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2);
mdelay(10);
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2,
RT5616_PWR_FV1 | RT5616_PWR_FV2);
snd_soc_update_bits(codec, RT5616_D_MISC,
RT5616_D_GATE_EN,
RT5616_D_GATE_EN);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, RT5616_D_MISC, RT5616_D_GATE_EN, 0);
snd_soc_write(codec, RT5616_PWR_DIG1, 0x0000);
snd_soc_write(codec, RT5616_PWR_DIG2, 0x0000);
snd_soc_write(codec, RT5616_PWR_VOL, 0x0000);
snd_soc_write(codec, RT5616_PWR_MIXER, 0x0000);
snd_soc_write(codec, RT5616_PWR_ANLG1, 0x0000);
snd_soc_write(codec, RT5616_PWR_ANLG2, 0x0000);
break;
default:
break;
}
return 0;
}
开发者ID:AshishNamdev，项目名称:linux，代码行数:64，代码来源:rt5616.c
示例17: wm0010_boot_xfer_complete
static void wm0010_boot_xfer_complete(void *data)
{
struct wm0010_boot_xfer *xfer = data;
struct snd_soc_codec *codec = xfer->codec;
struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
u32 *out32 = xfer->t.rx_buf;
int i;
if (xfer->m.status != 0) {
dev_err(codec->dev, "SPI transfer failed: %d\n",
xfer->m.status);
wm0010_mark_boot_failure(wm0010);
if (xfer->done)
complete(xfer->done);
return;
}
for (i = 0; i < xfer->t.len / 4; i++) {
dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
switch (be32_to_cpu(out32[i])) {
case 0xe0e0e0e0:
dev_err(codec->dev,
"%d: ROM error reported in stage 2\n", i);
wm0010_mark_boot_failure(wm0010);
break;
case 0x55555555:
if (wm0010->state < WM0010_STAGE2)
break;
dev_err(codec->dev,
"%d: ROM bootloader running in stage 2\n", i);
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0000:
dev_dbg(codec->dev, "Stage2 loader running\n");
break;
case 0x0fed0007:
dev_dbg(codec->dev, "CODE_HDR packet received\n");
break;
case 0x0fed0008:
dev_dbg(codec->dev, "CODE_DATA packet received\n");
break;
case 0x0fed0009:
dev_dbg(codec->dev, "Download complete\n");
break;
case 0x0fed000c:
dev_dbg(codec->dev, "Application start\n");
break;
case 0x0fed000e:
dev_dbg(codec->dev, "PLL packet received\n");
wm0010->pll_running = true;
break;
case 0x0fed0025:
dev_err(codec->dev, "Device reports image too long\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed002c:
dev_err(codec->dev, "Device reports bad SPI packet\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0031:
dev_err(codec->dev, "Device reports SPI read overflow\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0032:
dev_err(codec->dev, "Device reports SPI underclock\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0033:
dev_err(codec->dev, "Device reports bad header packet\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0034:
dev_err(codec->dev, "Device reports invalid packet type\n");
wm0010_mark_boot_failure(wm001
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