void __init sh73a0_add_standard_devices_dt(void)
{
	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };

	/* clocks are setup late during boot in the case of DT */
	sh73a0_clock_init();

	platform_add_devices(sh73a0_devices_dt,
			     ARRAY_SIZE(sh73a0_devices_dt));
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	/* Instantiate cpufreq-cpu0 */
	platform_device_register_full(&devinfo);
}

static const char *sh73a0_boards_compat_dt[] __initdata = {
	"renesas,sh73a0",
	NULL,
};

DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
	.smp		= smp_ops(sh73a0_smp_ops),
	.map_io		= sh73a0_map_io,
	.init_early	= sh73a0_init_delay,
	.nr_irqs	= NR_IRQS_LEGACY,
	.init_machine	= sh73a0_add_standard_devices_dt,
	.dt_compat	= sh73a0_boards_compat_dt,
MACHINE_END

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/init.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>

#include <asm/mach/arch.h>

#include "common.h"

static void __init msm_dt_init(void)
{
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char * const msm8960_dt_match[] __initconst = {
	"qcom,msm8960-cdp",
	NULL
};

DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
	.smp = smp_ops(msm_smp_ops),
	.map_io = msm_map_msm8960_io,
	.init_irq = irqchip_init,
	.init_time	= msm_dt_timer_init,
	.init_machine = msm_dt_init,
	.dt_compat = msm8960_dt_match,
MACHINE_END

};
#endif

void __init mt_map_io(void)
{
	iotable_init(mt_io_desc, ARRAY_SIZE(mt_io_desc));
}

static void __init mt_dt_init_irq(void)
{
            irqchip_init();
            mt_init_irq();
}



#ifdef CONFIG_OF
DT_MACHINE_START(MT6580_DT, "MT6580")
	.map_io		= mt_map_io,
	.smp		= smp_ops(mt_smp_ops),
	/*.init_irq	= mt_dt_init_irq,*/
	/*.init_time	= mt_timer_init,*/
	.init_machine	= mt_init,
	//  .fixup		= mt_dt_fixup,
	/* FIXME: need to implement the restart function */
	.restart	= arm_machine_restart,
	.reserve	= mt_reserve,
  .dt_compat  = mt_dt_match,
MACHINE_END
#endif

// ARM10C 20131005
// ARM10C 20131012
/*
//static const struct machine_desc __mach_desc_EXYNOS5_DT	\
// __used							\
// __attribute__((__section__(".arch.info.init"))) = {	\
//	.nr		= ~0,				\
//	.name		= "SAMSUNG EXYNOS5 (Flattened Device Tree)",
//	.smp		= smp_ops(exynos_smp_ops),
//	.map_io		= exynos_init_io,
//	.init_machine	= exynos5_dt_machine_init,
//	.init_late	= exynos_init_late,
//	.init_time	= exynos_init_time,
//	.dt_compat	= exynos5_dt_compat,
//	.restart        = exynos5_restart,
//	.reserve	= exynos5_reserve,
// };
*/
DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
	/* Maintainer: Kukjin Kim <[email protected]> */
	.smp		= smp_ops(exynos_smp_ops),
	// ARM10C 20131116
	.map_io		= exynos_init_io,
	.init_machine	= exynos5_dt_machine_init,
	.init_late	= exynos_init_late,
	.init_time	= exynos_init_time,
	.dt_compat	= exynos5_dt_compat,
	.restart        = exynos5_restart,
	.reserve	= exynos5_reserve,
MACHINE_END

	platform_device_register(&v2m_flash_device);
	platform_device_register(&v2m_cf_device);
	platform_device_register(&v2m_eth_device);
	platform_device_register(&v2m_usb_device);

	for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
		amba_device_register(v2m_amba_devs[i], &iomem_resource);

	pm_power_off = v2m_power_off;

	ct_desc->init_tile();
}

MACHINE_START(VEXPRESS, "ARM-Versatile Express")
	.atag_offset	= 0x100,
	.smp		= smp_ops(vexpress_smp_ops),
	.map_io		= v2m_map_io,
	.init_early	= v2m_init_early,
	.init_irq	= v2m_init_irq,
	.timer		= &v2m_timer,
	.handle_irq	= gic_handle_irq,
	.init_machine	= v2m_init,
	.restart	= v2m_restart,
MACHINE_END

static struct map_desc v2m_rs1_io_desc __initdata = {
	.virtual	= V2M_PERIPH,
	.pfn		= __phys_to_pfn(0x1c000000),
	.length		= SZ_2M,
	.type		= MT_DEVICE,
};

	gpio_request(GPIO_FN_SD0_WP, NULL);

	/* HSPI 0 */
	gpio_request(GPIO_FN_HSPI_CLK0,	NULL);
	gpio_request(GPIO_FN_HSPI_CS0,	NULL);
	gpio_request(GPIO_FN_HSPI_TX0,	NULL);
	gpio_request(GPIO_FN_HSPI_RX0,	NULL);

	/* USB (CN21) */
	gpio_request(GPIO_FN_USB_OVC0, NULL);
	gpio_request(GPIO_FN_USB_OVC1, NULL);
	gpio_request(GPIO_FN_USB_OVC2, NULL);

	/* USB (CN22) */
	gpio_request(GPIO_FN_USB_PENC2, NULL);

	r8a7779_add_standard_devices();
	platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}

MACHINE_START(MARZEN, "marzen")
	.smp		= smp_ops(r8a7779_smp_ops),
	.map_io		= r8a7779_map_io,
	.init_early	= r8a7779_add_early_devices,
	.nr_irqs	= NR_IRQS_LEGACY,
	.init_irq	= r8a7779_init_irq,
	.init_machine	= marzen_init,
	.init_late	= marzen_init_late,
	.init_time	= r8a7779_earlytimer_init,
MACHINE_END

	},
};

static void __init sh73a0_map_io(void)
{
	debug_ll_io_init();
	iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
}

static void __init sh73a0_generic_init(void)
{
#ifdef CONFIG_CACHE_L2X0
	/* Shared attribute override enable, 64K*8way */
	l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif
}

static const char *const sh73a0_boards_compat_dt[] __initconst = {
	"renesas,sh73a0",
	NULL,
};

DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
	.smp		= smp_ops(sh73a0_smp_ops),
	.map_io		= sh73a0_map_io,
	.init_early	= shmobile_init_delay,
	.init_machine	= sh73a0_generic_init,
	.init_late	= shmobile_init_late,
	.dt_compat	= sh73a0_boards_compat_dt,
MACHINE_END

 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/irqchip.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/smp.h>

#include <asm/mach/arch.h>

static void __init virt_init(void)
{
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char *virt_dt_match[] = {
	"linux,dummy-virt",
	"xen,xenvm",
	NULL
};

extern struct smp_operations virt_smp_ops;

DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
	.init_irq	= irqchip_init,
	.init_machine	= virt_init,
	.smp		= smp_ops(virt_smp_ops),
	.dt_compat	= virt_dt_match,
MACHINE_END

	if (!np) {
		pr_err("failed to find hisilicon,sysctrl node\n");
		return;
	}
	base = of_iomap(np, 0);
	if (!base) {
		pr_err("failed to map address in hisilicon,sysctrl node\n");
		return;
	}
	if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
		pr_err("failed to find reboot-offset property\n");
		return;
	}
	writel_relaxed(0xdeadbeef, base + offset);

	while (1)
		cpu_do_idle();
}

static const char *hi3xxx_compat[] __initconst = {
	"hisilicon,hi3620-hi4511",
	NULL,
};

DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
	.map_io		= hi3620_map_io,
	.dt_compat	= hi3xxx_compat,
	.smp		= smp_ops(hi3xxx_smp_ops),
	.restart	= hi3xxx_restart,
MACHINE_END

#endif
};

void __init mt_map_io(void)
{
    iotable_init(mt_io_desc, ARRAY_SIZE(mt_io_desc));
}

#ifdef CONFIG_MTK_TABLET_HARDWARE
MACHINE_START(MT8127, "MT8117")
#else
MACHINE_START(MT8127, "MT8127")
#endif
    .atag_offset    = 0x00000100,
    .map_io         = mt_map_io,
    .init_irq       = mt_init_irq,
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
    .timer          = &mt6582_timer,
#else
    .smp            = smp_ops(mt65xx_smp_ops),
    .init_time      = mt6582_timer_init,
#endif
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || defined(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT)
    .init_early     = mt_init_early,
#endif
    .init_machine   = mt_init,
    .fixup          = mt_fixup,
    .restart        = arm_machine_restart,
    .reserve        = mt_reserve,
MACHINE_END

			ARMADA_370_XP_MBUS_WINS_SIZE,
			ARMADA_370_XP_SDRAM_WINS_BASE,
			ARMADA_370_XP_SDRAM_WINS_SIZE);

#ifdef CONFIG_CACHE_L2X0
	l2x0_of_init(0, ~0UL);
#endif
}

static void __init armada_370_xp_dt_init(void)
{
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	coherency_init();
}

static const char * const armada_370_xp_dt_compat[] = {
	"marvell,armada-370-xp",
	NULL,
};

DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
	.smp		= smp_ops(armada_xp_smp_ops),
	.init_machine	= armada_370_xp_dt_init,
	.map_io		= armada_370_xp_map_io,
	.init_early	= armada_370_xp_init_early,
	.init_irq	= irqchip_init,
	.init_time	= armada_370_xp_timer_and_clk_init,
	.restart	= mvebu_restart,
	.dt_compat	= armada_370_xp_dt_compat,
MACHINE_END

 */
static const struct clk_name clk_names[] __initconst = {
	{ "du0", "du.0", "rcar-du-r8a7791" },
	{ "du1", "du.1", "rcar-du-r8a7791" },
	{ "lvds0", "lvds.0", "rcar-du-r8a7791" },
};

static void __init koelsch_add_standard_devices(void)
{
	shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	koelsch_add_du_device();
}

static const char * const koelsch_boards_compat_dt[] __initconst = {
	"renesas,koelsch",
	"renesas,koelsch-reference",
	NULL,
};

DT_MACHINE_START(KOELSCH_DT, "koelsch")
	.smp		= smp_ops(r8a7791_smp_ops),
	.init_early	= shmobile_init_delay,
	.init_time	= rcar_gen2_timer_init,
	.init_machine	= koelsch_add_standard_devices,
	.init_late	= shmobile_init_late,
	.reserve	= rcar_gen2_reserve,
	.dt_compat	= koelsch_boards_compat_dt,
MACHINE_END

	writel(0, SEC_CTRL_ALTERNATIVE_SEL);
	writel(0, SEC_CTRL_PULLUP_SEL);

	/* No need to save any state, as the ROM loader can determine whether
	 * reset is due to power cycling or programatic action, just hit the
	 * (self-clearing) CPU reset bit of the block reset register */
	value =
		BIT(SYS_CTRL_RST_SCU) |
		BIT(SYS_CTRL_RST_ARM0) |
		BIT(SYS_CTRL_RST_ARM1);

	writel(value, SYS_CTRL_RST_SET_CTRL);
}

static const char * const ox820_dt_board_compat[] = {
	"plxtech,nas7820",
	"plxtech,nas7821",
	"plxtech,nas7825",
	NULL
};

DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)")
	.map_io		= ox820_map_common_io,
	.smp		= smp_ops(ox820_smp_ops),
	.init_early	= ox820_init_early,
	.init_time	= ox820_timer_init,
	.init_machine	= ox820_dt_init,
	.restart	= ox820_assert_system_reset,
	.dt_compat	= ox820_dt_board_compat,
MACHINE_END

}

void __init emev2_init_delay(void)
{
	shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
}

static void __init emev2_add_standard_devices_dt(void)
{
#ifdef CONFIG_COMMON_CLK
	of_clk_init(NULL);
#else
	emev2_clock_init();
#endif
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char *emev2_boards_compat_dt[] __initdata = {
	"renesas,emev2",
	NULL,
};

DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
	.smp		= smp_ops(emev2_smp_ops),
	.map_io		= emev2_map_io,
	.init_early	= emev2_init_delay,
	.init_machine	= emev2_add_standard_devices_dt,
	.init_late	= shmobile_init_late,
	.dt_compat	= emev2_boards_compat_dt,
MACHINE_END

};

/*
 * Following will create 16MB static virtual/physical mappings
 * PHYSICAL		VIRTUAL
 * 0xD8000000		0xFA000000
 */
struct map_desc spear1310_io_desc[] __initdata = {
	{
		.virtual	= VA_SPEAR1310_RAS_GRP1_BASE,
		.pfn		= __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	},
};

static void __init spear1310_map_io(void)
{
	iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
	spear13xx_map_io();
}

DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
	.smp		=	smp_ops(spear13xx_smp_ops),
	.map_io		=	spear1310_map_io,
	.init_time	=	spear13xx_timer_init,
	.init_machine	=	spear1310_dt_init,
	.restart	=	spear_restart,
	.dt_compat	=	spear1310_dt_board_compat,
MACHINE_END

void __init stih41x_l2x0_init(void)
{
	u32 way_size = 0x4;
	u32 aux_ctrl;
	/* may be this can be encoded in macros like BIT*() */
	aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
		(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
		(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
		(way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);

	l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
}

static void __init stih41x_machine_init(void)
{
	stih41x_l2x0_init();
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char *stih41x_dt_match[] __initdata = {
	"st,stih415",
	"st,stih416",
	NULL
};

DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
	.init_machine	= stih41x_machine_init,
	.smp		= smp_ops(sti_smp_ops),
	.dt_compat	= stih41x_dt_match,
MACHINE_END

	if (phys) {
		memblock_remove(phys, SZ_1M);
		memblock_reserve(phys, SZ_1M);
		ramoops_phys_addr = phys;
		ramoops_mem_size = SZ_1M;
	} else {
		ramoops_phys_addr = 0;
		ramoops_mem_size = 0;
		pr_err("no memory reserve for ramoops.\n");
	}
#endif
	return;
}

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	/*
	 * i.MX6Q/DL maps system memory at 0x10000000 (offset 256MiB), and
	 * GPU has a limit on physical address that it accesses, which must
	 * be below 2GiB.
	 */
	.dma_zone_size	= (SZ_2G - SZ_256M),
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	 = imx6q_dt_compat,
	.reserve     = imx6q_reserve,
	.restart	= mxc_restart,
MACHINE_END

	/* disable remap */
	writel_relaxed(1 << (12 + 16), RK_GRF_VIRT + RK3188_GRF_SOC_CON0);
	/* pll enter slow mode */
	writel_relaxed(RK3188_PLL_MODE_SLOW(RK3188_APLL_ID) |
		       RK3188_PLL_MODE_SLOW(RK3188_CPLL_ID) |
		       RK3188_PLL_MODE_SLOW(RK3188_GPLL_ID),
		       RK_CRU_VIRT + RK3188_CRU_MODE_CON);
	dsb();
	writel_relaxed(0xeca8, RK_CRU_VIRT + RK3188_CRU_GLB_SRST_SND);
	dsb();
}
#ifdef CONFIG_PM
static void __init rk3188_init_suspend(void);
#endif
DT_MACHINE_START(RK3188_DT, "RK30board")
	.smp		= smp_ops(rockchip_smp_ops),
	.map_io		= rk3188_dt_map_io,
	.init_time	= rk3188_dt_init_timer,
	.dt_compat	= rk3188_dt_compat,
#ifdef CONFIG_PM
	.init_late	= rk3188_init_suspend,
#endif
	.reserve	= rk3188_reserve,
	.restart	= rk3188_restart,
MACHINE_END

#define CPU 3188
char PIE_DATA(sram_stack)[1024];
EXPORT_PIE_SYMBOL(DATA(sram_stack));

static int __init rk3188_pie_init(void)

 * bounce on and off after each packet, which we apparently want to avoid.
 */
static int lager_ksz8041_fixup(struct phy_device *phydev)
{
	u16 phyctrl1 = phy_read(phydev, 0x1e);

	phyctrl1 &= ~0xc000;
	phyctrl1 |= 0x4000;
	return phy_write(phydev, 0x1e, phyctrl1);
}

static void __init lager_init(void)
{
	lager_add_standard_devices();

	phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
}

static const char * const lager_boards_compat_dt[] __initconst = {
	"renesas,lager",
	NULL,
};

DT_MACHINE_START(LAGER_DT, "lager")
	.smp		= smp_ops(r8a7790_smp_ops),
	.init_early	= r8a7790_init_early,
	.init_time	= rcar_gen2_timer_init,
	.init_machine	= lager_init,
	.dt_compat	= lager_boards_compat_dt,
MACHINE_END

#endif

#ifdef CONFIG_ARCH_PRIMA2
static const char *const prima2_dt_match[] __initconst = {
	"sirf,prima2",
	NULL
};

DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
	/* Maintainer: Barry Song <[email protected]> */
	.l2c_aux_val	= 0,
	.l2c_aux_mask	= ~0,
	.dma_zone_size	= SZ_256M,
	.init_late	= sirfsoc_init_late,
	.dt_compat      = prima2_dt_match,
MACHINE_END
#endif

#ifdef CONFIG_ARCH_ATLAS7
static const char *const atlas7_dt_match[] __initconst = {
	"sirf,atlas7",
	NULL
};

DT_MACHINE_START(ATLAS7_DT, "Generic ATLAS7 (Flattened Device Tree)")
	/* Maintainer: Barry Song <[email protected]> */
	.smp            = smp_ops(sirfsoc_smp_ops),
	.dt_compat      = atlas7_dt_match,
MACHINE_END
#endif