int
avm_dump_sections(int verbose)
{
  struct mm_section_t **p;
  int i, j, len;

  sim_printf("mm_sect_count: %d\n", mm_sect_count);
  for (i = 0, p = mm_sects; i < mm_sect_count; ++i, ++p)
    {
      sim_printf("mm_sects[%d]: {range: 0x%08x-0x%08x, flags: 0x%08x, name:\"%s\" }",
        i, (*p)->base, (*p)->end-1, (*p)->flags, (*p)->name);

      if (verbose == 0)
        len = 0;
      else
        len = (*p)->end - (*p)->base;

      for (j = 0; j < len; j += 4)
        {
          if ((j & 15) == 0)
            sim_printf("\n# %08x:", j + (*p)->base);
          sim_printf(" %08x", *(unsigned32*)((*p)->data + j));
        }

      sim_printf("\n");
    }
}

t_stat cable_disk (int disk_unit_num, int iom_unit_num, int chan_num, int dev_code)
  {
    if (disk_unit_num < 0 || disk_unit_num >= (int) disk_dev . numunits)
      {
        // sim_debug (DBG_ERR, & sys_dev, "cable_disk: disk_unit_num out of range <%d>\n", disk_unit_num);
        sim_printf ("cable_disk: disk_unit_num out of range <%d>\n", disk_unit_num);
        return SCPE_ARG;
      }

    if (cables_from_ioms_to_disk [disk_unit_num] . iom_unit_num != -1)
      {
        // sim_debug (DBG_ERR, & sys_dev, "cable_disk: socket in use\n");
        sim_printf ("cable_disk: socket in use\n");
        return SCPE_ARG;
      }

    // Plug the other end of the cable in
    t_stat rc = cable_to_iom (iom_unit_num, chan_num, dev_code, DEVT_DISK, chan_type_PSI, disk_unit_num, & disk_dev, & disk_unit [disk_unit_num], disk_iom_cmd);
    if (rc)
      return rc;

    cables_from_ioms_to_disk [disk_unit_num] . iom_unit_num = iom_unit_num;
    cables_from_ioms_to_disk [disk_unit_num] . chan_num = chan_num;
    cables_from_ioms_to_disk [disk_unit_num] . dev_code = dev_code;

    return SCPE_OK;
  }

int32 i8259b1(int32 io, int32 data)
{
    if (io == 0) {                      /* read data port */
        return (i8259_unit[1].u5);              /* IMR */
    } else {                            /* write data port */
        if (icw_num1 >= 2 && icw_num1 < 5) { /* ICW mode */                  
            switch (icw_num1) {
            case 2:                     /* ICW2 */
                i8259_icw2[1] = data;
                break;
            case 3:                     /* ICW3 */
                i8259_icw3[1] = data;
                break;
            case 4:                     /* ICW4 */
                if (i8259_icw1[1] & 0x01)
                    i8259_icw4[1] = data;
                else
                    sim_printf("8259b-1: ICW4 not enabled - data=%02X\n", data);
                break;
            default:
                sim_printf("8259b-1: ICW Error %02X\n", data);
                break;
            }
            icw_num1++;
        } else {
            i8259_ocw1[1] = data;       /* OCW0 */
        }
    }
    i8259_dump(1);
    return 0;
}

t_stat i8259_reset (DEVICE *dptr, int32 base)
{
    switch (i8259_cnt) {
    case 0:
        reg_dev(i8259a0, base); 
        reg_dev(i8259b0, base + 1); 
        reg_dev(i8259a0, base + 2); 
        reg_dev(i8259b0, base + 3); 
        i8259_unit[0].u3 = 0x00; /* IRR */
        i8259_unit[0].u4 = 0x00; /* ISR */
        i8259_unit[0].u5 = 0x00; /* IMR */
        sim_printf("   8259-0: Reset\n");
        break;
    case 1:
        reg_dev(i8259a1, base); 
        reg_dev(i8259b1, base + 1); 
        reg_dev(i8259a1, base + 2); 
        reg_dev(i8259b1, base + 3); 
        i8259_unit[1].u3 = 0x00; /* IRR */
        i8259_unit[1].u4 = 0x00; /* ISR */
        i8259_unit[1].u5 = 0x00; /* IMR */
        sim_printf("   8259-1: Reset\n");
        break;
    default:
        sim_printf("   8259: Bad device\n");
        break;
    }
    sim_printf("   8259-%d: Registered at %02X\n", i8259_cnt, base);
    i8259_cnt++;
    return SCPE_OK;
}

t_stat qty_attach( UNIT * unitp, char * cptr )
    {
    t_stat  r ;
    int a ;

    /*  switches:   A       auto-disconnect
     *              M       modem control
     */

    qty_mdm = qty_auto = 0;                             /* modem ctl off */
    r = tmxr_attach( &qty_desc, unitp, cptr ) ;         /* attach QTY */
    if ( r != SCPE_OK )
        {
        return ( r ) ;                                  /* error! */
        }
    if ( sim_switches & SWMASK('M') )                   /* modem control? */
        {
        qty_mdm = 1;
        sim_printf( "Modem control activated\n" ) ;
        if ( sim_switches & SWMASK ('A') )              /* autodisconnect? */
            {
            qty_auto = 1 ;
            sim_printf( "Auto disconnect activated\n" ) ;
            }
        }
    qty_polls = 0 ;
    for ( a = 0 ; a < QTY_MAX ; ++a )
        {
        /*  QTY lines are always enabled - force RX and TX to 'enabled' */
        qty_status[ a ] = (QTY_L_RXE | QTY_L_TXE) ;
        }
    sim_activate( unitp, tmxr_poll ) ;
    return ( SCPE_OK ) ;
    }   /*  end of 'qty_attach'  */

int32 i8259a1(int32 io, int32 data)
{
    if (io == 0) {                      /* read data port */
        if ((i8259_ocw3[1] & 0x03) == 0x02)
            return (i8259_unit[1].u3);  /* IRR */
        if ((i8259_ocw3[1] & 0x03) == 0x03)
            return (i8259_unit[1].u4);  /* ISR */
    } else {                            /* write data port */
        if (data & 0x10) {
            icw_num1 = 1;
        }
        if (icw_num1 == 1) {
            i8259_icw1[1] = data;       /* ICW1 */
            i8259_unit[1].u5 = 0x00;    /* clear IMR */
            i8259_ocw3[1] = 0x02;       /* clear OCW3, Sel IRR */
        } else {
            switch (data & 0x18) {
            case 0:                     /* OCW2 */
                i8259_ocw2[1] = data;
                break;
            case 8:                     /* OCW3 */
                i8259_ocw3[1] = data;
                break;
            default:
                sim_printf("8259b-1: OCW Error %02X\n", data);
                break;
            }
        }
        sim_printf("8259a-1: data = %02X\n", data);
        icw_num1++;                     /* step ICW number */
    }
    i8259_dump(1);
    return 0;
}

uint8 isbc202(t_bool io, uint8 data, uint8 devnum)
{
    if (io == 0) {                      /* always return 0 */
        sim_printf("   isbc202: read data=%02X port=%02X returned 0\n", data, devnum);
        return 0x00;
    } else {                            /* write control port */
        sim_printf("   isbc202: data=%02X port=%02X\n", data, devnum);
    }
}

uint8 ioc_cont(t_bool io, uint8 data, uint8 devnum)
{
    if (io == 0) {                      /* read status port */
        sim_printf("   ioc_cont: read data=%02X port=%02X returned 0x00 from PC=%04X\n", data, devnum, saved_PC);
        return 0x00;
    } else {                            /* write control port */
        sim_printf("   ioc_cont: data=%02X port=%02X\n", data, devnum);
    }
}

t_stat ioc_cont_reset(DEVICE *dptr, uint16 base, uint8 devnum)
{
    reg_dev(ioc_cont, base, devnum); 
    reg_dev(ioc_cont, base + 1, devnum); 
    ioc_cont_unit[devnum].u3 = 0x00; /* ipc reset */
    sim_printf("   ioc_cont[%d]: Reset\n", devnum);
    sim_printf("   ioc_cont[%d]: Registered at %04X\n", devnum, base);
    return SCPE_OK;
}

static void showdata(int32 isRead) {
    int32 i;
    sim_printf("MDSAD: " ADDRESS_FORMAT " %s Sector =" NLP "\t", PCX, isRead ? "Read" : "Write");
    for(i=0; i < MDSAD_SECTOR_LEN; i++) {
        sim_printf("%02X ", sdata.u.data[i]);
        if(((i+1) & 0xf) == 0)
            sim_printf(NLP "\t");
    }
    sim_printf(NLP);
}

uint16 reg_dev(uint8 (*routine)(t_bool io, uint8 data), uint16 port)
{
    if (dev_table[port].routine != &nulldev) {  /* port already assigned */
        sim_printf("xtbus: I/O Port %03X is already assigned\n", port);
    } else {
        sim_printf("Port %03X is assigned\n", port);
        dev_table[port].routine = routine;
    }
    //dump_dev_table();
    return port;
}

/* Attach routine */
static t_stat mdsad_attach(UNIT *uptr, CONST char *cptr)
{
    char header[4];
    t_stat r;
    unsigned int i = 0;

    r = attach_unit(uptr, cptr);    /* attach unit  */
    if(r != SCPE_OK)                /* error?       */
        return r;

    /* Determine length of this disk */
    if(sim_fsize(uptr->fileref) != 0) {
        uptr->capac = sim_fsize(uptr->fileref);
    } else {
        uptr->capac = MDSAD_CAPACITY;
    }

    for(i = 0; i < MDSAD_MAX_DRIVES; i++) {
        mdsad_info->drive[i].uptr = &mdsad_dev.units[i];
    }

    for(i = 0; i < MDSAD_MAX_DRIVES; i++) {
        if(mdsad_dev.units[i].fileref == uptr->fileref) {
            break;
        }

    mdsad_info->orders.st = 0;      /* ensure valid state */
    }

    /* Default for new file is DSK */
    uptr->u3 = IMAGE_TYPE_DSK;

    if(uptr->capac > 0) {
        char *rtn = fgets(header, 4, uptr->fileref);
        if((rtn != NULL) && (strncmp(header, "CPT", 3) == 0)) {
            sim_printf("CPT images not yet supported\n");
            uptr->u3 = IMAGE_TYPE_CPT;
            mdsad_detach(uptr);
            return SCPE_OPENERR;
        } else {
            uptr->u3 = IMAGE_TYPE_DSK;
        }
    }

    if (uptr->flags & UNIT_MDSAD_VERBOSE)
        sim_printf("MDSAD%d, attached to '%s', type=%s, len=%d\n", i, cptr,
            uptr->u3 == IMAGE_TYPE_CPT ? "CPT" : "DSK",
            uptr->capac);

    return SCPE_OK;
}

t_stat sim_load_bin (FILE *fi)
{
int32 hi, lo, wd, csum, t;
uint32 field, newf, origin;
int32 sections_read = 0;

for (;;) {
    csum = origin = field = newf = 0;                   /* init */
    do {                                                /* skip leader */
        if ((hi = sim_bin_getc (fi, &newf)) == EOF) {
            if (sections_read != 0) {
                sim_printf ("%d sections sucessfully read\n\r", sections_read);
                return SCPE_OK;
                } 
            else
                return SCPE_FMT;
            }
        } while ((hi == 0) || (hi >= 0200));
    for (;;) {                                          /* data blocks */
        if ((lo = sim_bin_getc (fi, &newf)) == EOF)     /* low char */
            return SCPE_FMT;
        wd = (hi << 6) | lo;                            /* form word */
        t = hi;                                         /* save for csum */
        if ((hi = sim_bin_getc (fi, &newf)) == EOF)     /* next char */
            return SCPE_FMT;
        if (hi == 0200) {                               /* end of tape? */
            if ((csum - wd) & 07777) {                  /* valid csum? */
                if (sections_read != 0)
                    sim_printf ("%d sections sucessfully read\n\r", sections_read);
                return SCPE_CSUM;
                }
            if (!(sim_switches & SWMASK ('A')))        /* Load all sections? */
                return SCPE_OK;
            sections_read++;
            break;
            }
        csum = csum + t + lo;                           /* add to csum */
        if (wd > 07777)                                 /* chan 7 set? */
            origin = wd & 07777;                        /* new origin */
        else {                                          /* no, data */
            if ((field | origin) >= MEMSIZE) 
                return SCPE_NXM;
            M[field | origin] = wd;
            origin = (origin + 1) & 07777;
            }
        field = newf;                                   /* update field */
        }
    }
return SCPE_IERR;
}

t_stat i8272_reset(DEVICE *dptr, uint16 base)
{
    if (i8272_devnum >= i8272_NUM) {
        sim_printf("8251_reset: too many devices!\n");
        return 0;
    }
    i8272_reset1(i8272_devnum);
    sim_printf("   8251-%d: Registered at %03X\n", i8272_devnum, base);
    i8272_port[i8272_devnum] = reg_dev(i8251d, base); 
    reg_dev(i8251s, base + 1); 
    i8272_unit[i8272_devnum].u6 = i8272_devnum;
    sim_activate(&i8272_unit[i8272_devnum], i8272_unit[i8272_devnum].wait); /* activate unit */
    i8272_devnum++;
    return SCPE_OK;
}

t_stat EPROM_reset (DEVICE *dptr, uint32 base, uint32 size)
{
    sim_debug (DEBUG_flow, &EPROM_dev, "   EPROM_reset: base=%05X size=%05X\n", base, size);
    if ((EPROM_unit.flags & UNIT_ATT) == 0) { /* if unattached */
        EPROM_unit.capac = size;        /* set EPROM size */
        EPROM_unit.u3 = base;           /* set EPROM base addr */
        sim_debug (DEBUG_flow, &EPROM_dev, "Done1\n");
        sim_printf("   EPROM: Available [%05X-%05XH]\n", 
            base, size);
        return SCPE_OK;
    } else
        sim_printf("EPROM: No file attached\n");
    sim_debug (DEBUG_flow, &EPROM_dev, "Done2\n");
    return SCPE_OK;
}

t_stat isbc202_reset(DEVICE *dptr, uint16 base, uint8 devnum)
{
    reg_dev(isbc202, base, devnum);
    reg_dev(isbc202, base + 1, devnum);
    reg_dev(isbc202, base + 2, devnum);
    reg_dev(isbc202, base + 3, devnum);
    reg_dev(isbc202, base + 4, devnum);
    reg_dev(isbc202, base + 5, devnum);
    reg_dev(isbc202, base + 6, devnum);
    reg_dev(isbc202, base + 7, devnum);
    isbc202_unit[devnum].u3 = 0x00; /* ipc reset */
    sim_printf("   isbc202-%d: Reset\n", devnum);
    sim_printf("   isbc202-%d: Registered at %04X\n", devnum, base);
    return SCPE_OK;
}

/* channel A command/status */
int32 i8274As(int32 io, int32 data)
{
    if (io == 0) {                      /* read status port */
        switch(wr0a & 0x7) {
            case 0:                     /* rr0a */
                return rr0a;
            case 1:                     /* rr1a */
                return rr1a;
            case 2:                     /* rr1a */
                return rr2a;
        }
        return 0;                       /* bad register select */
    } else {                            /* write status port */
        switch(wr0a & 0x7) {
            case 0:                     /* wr0a */
                wr0a = data;
                if ((wr0a & 0x38) == 0x18) { /* channel reset */
                    wr0a = wr1a = wr2a = wr3a = wr4a = wr5a = 0;
                    wr6a = wr7a = rr0a = rr1a = rr2a = 0;
                    sim_printf("8274 Channel A reset\n");
                }
                break;
            case 1:                     /* wr1a */
                wr1a = data;
                break;
            case 2:                     /* wr2a */
                wr2a = data;
                break;
            case 3:                     /* wr3a */
                wr3a = data;
                 break;
            case 4:                     /* wr4a */
                wr4a = data;
                 break;
            case 5:                     /* wr5a */
                wr5a = data;
                break;
            case 6:                     /* wr6a */
                wr6a = data;
                break;
            case 7:                     /* wr7a */
                wr7a = data;
                break;
        }
        sim_printf("8274 Command WR%dA=%02X\n", wr0a & 0x7, data);
        return 0;
    }
}

t_stat i8274_reset (DEVICE *dptr)
{
    wr0a = wr1a = wr2a = wr3a = wr4a = wr5a = wr6a = wr7a = rr0a = rr1a = rr2a = 0;
    wr0b = wr1b = wr2b = wr3b = wr4b = wr5b = wr6b = wr7b = rr0b = rr1b = rr2b = 0;
    sim_printf("   8274 Reset\n");
    return SCPE_OK;
}

static
t_stat Test (FILE UNUSED *st, UNIT UNUSED *uptr, int32 UNUSED val, void UNUSED *desc)
{
    sim_printf("Test: IPC not enabled.\n");
    
    return ipc(ipcTest, 0, 0, 0, 0);
}

static t_stat ipc_set_node (UNIT UNUSED *uptr, int32 UNUSED val, char *cval, void UNUSED *desc)
{
    if (cval == NULL || *cval == 0)
    {
        strcpy(fnpName, IPC_NODE);
#ifdef VM_FNP
        set_prompt (0, "sim>");     // reset prompt to default
#endif
    }
    else
    {
        stripquotes(cval);
        
        if (!startsWith(cval, "cpu"))
            sim_printf("WARNING: Node name <%s> does not begin with 'cpu'\n", cval);
        
        strcpy(fnpName, cval);
#ifdef VM_FNP
        char temp[132];
        sprintf(temp, "%s>", fnpName);
        set_prompt(0, temp);
#endif
        
    }
    
    // if IPC is already running, resrart it with new node
    if (actor)
    {
        ipc(ipcStop, 0, 0, 0, 0);    // ki;; IPC
        ipc(ipcStart, fnpName, 0, 0, 0);
    }
    
    return SCPE_OK;
}