static void __init ar7_irq_init(int base)
{
	int i;
	/*
	 * Disable interrupts and clear pending
	 */
	writel(0xffffffff, REG(ECR_OFFSET(0)));
	writel(0xff, REG(ECR_OFFSET(32)));
	writel(0xffffffff, REG(SEC_ECR_OFFSET));
	writel(0xffffffff, REG(CR_OFFSET(0)));
	writel(0xff, REG(CR_OFFSET(32)));
	writel(0xffffffff, REG(SEC_CR_OFFSET));

	ar7_irq_base = base;

	for (i = 0; i < 40; i++) {
		writel(i, REG(CHNL_OFFSET(i)));
		/* Primary IRQ's */
		set_irq_chip_and_handler(base + i, &ar7_irq_type,
					 handle_level_irq);
		/* Secondary IRQ's */
		if (i < 32)
			set_irq_chip_and_handler(base + i + 40,
						 &ar7_sec_irq_type,
						 handle_level_irq);
	}

	setup_irq(2, &ar7_cascade_action);
	setup_irq(ar7_irq_base, &ar7_cascade_action);
	set_c0_status(IE_IRQ0);
}

void __init mips_cpu_irq_init(void)
{
	int irq_base = MIPS_CPU_IRQ_BASE;
	int i;

	/* Mask interrupts. */
	clear_c0_status(ST0_IM);
	clear_c0_cause(CAUSEF_IP);

	/*
	 * Only MT is using the software interrupts currently, so we just
	 * leave them uninitialized for other processors.
	 */
	if (cpu_has_mipsmt)
		for (i = irq_base; i < irq_base + 2; i++)
			set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
						 handle_percpu_irq);

#if defined(CONFIG_BMIPS4380) || defined(CONFIG_BMIPS5000)
	/* set up SW IRQs for SMP */
	for (i = irq_base; i < irq_base + 8; i++)
#else
	for (i = irq_base + 2; i < irq_base + 8; i++)
#endif
		set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
					 handle_percpu_irq);
}

void __init arch_init_irq(void)
{
	unsigned int i;

	set_irq_priority();

	/* clear interrupt counter for VPE0 and VPE1 */
	if (isRT6855A)
		tc_outl(CR_INTC_ITR, (1 << 18) | (1 << 10));

	/* Disable all hardware interrupts */
	clear_c0_status(ST0_IM);
	clear_c0_cause(CAUSEF_IP);

	/* Initialize IRQ action handlers */
	for (i = 0; i < NR_IRQS; i++) {
#ifdef CONFIG_MIPS_TC3262
		/*
	 	 * Only MT is using the software interrupts currently, so we just
	 	 * leave them uninitialized for other processors.
	 	 */
		if (cpu_has_mipsmt) {
			if ((i == SI_SWINT1_INT0) || (i == SI_SWINT1_INT1) ||
				(i == SI_SWINT_INT0) || (i == SI_SWINT_INT1)) { 
				set_irq_chip(i, &mips_mt_cpu_irq_controller);
				continue;
			}
		}

		if ((i == SI_TIMER_INT) || (i == SI_TIMER1_INT))
			set_irq_chip_and_handler(i, &tc3162_irq_chip,
					 handle_percpu_irq);
		else
			set_irq_chip_and_handler(i, &tc3162_irq_chip,
					 handle_level_irq);
#else
		set_irq_chip_and_handler(i, &tc3162_irq_chip,
					 handle_level_irq);
#endif
	}

#ifdef CONFIG_MIPS_TC3262
	if (cpu_has_veic || cpu_has_vint) {
		write_c0_status((read_c0_status() & ~ST0_IM ) |
			                (STATUSF_IP0 | STATUSF_IP1)); 

		/* register irq dispatch functions */
		for (i = 0; i < NR_IRQS; i++)
			set_vi_handler(i, irq_dispatch_tab[i]);
	} else {
		change_c0_status(ST0_IM, ALLINTS);
	}
#else
	/* Enable all interrupts */
	change_c0_status(ST0_IM, ALLINTS);
#endif
#ifdef CONFIG_MIPS_MT_SMP
	vsmp_int_init();
#endif
}

static int vlynq_setup_irq(struct vlynq_device *dev)
{
	u32 val;
	int i, virq;

	if (dev->local_irq == dev->remote_irq) {
		printk(KERN_ERR
		       "%s: local vlynq irq should be different from remote\n",
		       dev_name(&dev->dev));
		return -EINVAL;
	}

	/* Clear local and remote error bits */
	writel(readl(&dev->local->status), &dev->local->status);
	writel(readl(&dev->remote->status), &dev->remote->status);

	/* Now setup interrupts */
	val = VLYNQ_CTRL_INT_VECTOR(dev->local_irq);
	val |= VLYNQ_CTRL_INT_ENABLE | VLYNQ_CTRL_INT_LOCAL |
		VLYNQ_CTRL_INT2CFG;
	val |= readl(&dev->local->control);
	writel(VLYNQ_INT_OFFSET, &dev->local->int_ptr);
	writel(val, &dev->local->control);

	val = VLYNQ_CTRL_INT_VECTOR(dev->remote_irq);
	val |= VLYNQ_CTRL_INT_ENABLE;
	val |= readl(&dev->remote->control);
	writel(VLYNQ_INT_OFFSET, &dev->remote->int_ptr);
	writel(val, &dev->remote->int_ptr);
	writel(val, &dev->remote->control);

	for (i = dev->irq_start; i <= dev->irq_end; i++) {
		virq = i - dev->irq_start;
		if (virq == dev->local_irq) {
			set_irq_chip_and_handler(i, &vlynq_local_chip,
						 handle_level_irq);
			set_irq_chip_data(i, dev);
		} else if (virq == dev->remote_irq) {
			set_irq_chip_and_handler(i, &vlynq_remote_chip,
						 handle_level_irq);
			set_irq_chip_data(i, dev);
		} else {
			set_irq_chip_and_handler(i, &vlynq_irq_chip,
						 handle_simple_irq);
			set_irq_chip_data(i, dev);
			writel(0, &dev->remote->int_device[virq >> 2]);
		}
	}

	if (request_irq(dev->irq, vlynq_irq, IRQF_SHARED, "vlynq", dev)) {
		printk(KERN_ERR "%s: request_irq failed\n",
					dev_name(&dev->dev));
		return -EAGAIN;
	}

	return 0;
}

/**
 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
 */
static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
                               irq_hw_number_t irq)
{
    int l1irq;
    int l2irq;
    struct irq_chip *irqchip;
    void *hndlr;
    int type;
    u32 reg;

    l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
    l2irq = irq & MPC52xx_IRQ_L2_MASK;

    /*
     * External IRQs are handled differently by the hardware so they are
     * handled by a dedicated irq_chip structure.
     */
    if (mpc52xx_is_extirq(l1irq, l2irq)) {
        reg = in_be32(&intr->ctrl);
        type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
        if ((type == IRQ_TYPE_EDGE_FALLING) ||
                (type == IRQ_TYPE_EDGE_RISING))
            hndlr = handle_edge_irq;
        else
            hndlr = handle_level_irq;

        set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
        pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
                 __func__, l2irq, virq, (int)irq, type);
        return 0;
    }

    /* It is an internal SOC irq.  Choose the correct irq_chip */
    switch (l1irq) {
    case MPC52xx_IRQ_L1_MAIN:
        irqchip = &mpc52xx_main_irqchip;
        break;
    case MPC52xx_IRQ_L1_PERP:
        irqchip = &mpc52xx_periph_irqchip;
        break;
    case MPC52xx_IRQ_L1_SDMA:
        irqchip = &mpc52xx_sdma_irqchip;
        break;
    default:
        pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n",
               __func__, virq, l1irq, l2irq);
        return -EINVAL;
    }

    set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
    pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);

    return 0;
}

void __init rm9k_cpu_irq_init(void)
{
	int base = RM9K_CPU_IRQ_BASE;
	int i;

	clear_c0_intcontrol(0x0000f000);		/* Mask all */

	for (i = base; i < base + 4; i++)
		set_irq_chip_and_handler(i, &rm9k_irq_controller,
					 handle_level_irq);

	rm9000_perfcount_irq = base + 1;
	set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
				 handle_percpu_irq);
}

static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
				  irq_hw_number_t irq)
{
	set_irq_chip_data(virq, h->host_data);

	if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
	    xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
		set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip,
			handle_level_irq);
	} else {
		set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
			handle_edge_irq);
	}
	return 0;
}

int ia64_setup_msi_irq(unsigned int irq, struct pci_dev *pdev)
{
	struct msi_msg	msg;
	unsigned long	dest_phys_id;
	unsigned int	vector;

	dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map));
	vector = irq;

	msg.address_hi = 0;
	msg.address_lo =
		MSI_ADDR_HEADER |
		MSI_ADDR_DESTMODE_PHYS |
		MSI_ADDR_REDIRECTION_CPU |
		MSI_ADDR_DESTID_CPU(dest_phys_id);

	msg.data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		MSI_DATA_DELIVERY_FIXED |
		MSI_DATA_VECTOR(vector);

	write_msi_msg(irq, &msg);
	set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);

	return 0;
}

static int iseries_irq_host_map(struct irq_host *h, unsigned int virq,
				irq_hw_number_t hw)
{
	set_irq_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq);

	return 0;
}

void __init msp_cic_irq_init(void)
{
	int i;

	/* Mask/clear interrupts. */
	*CIC_VPE0_MSK_REG = 0x00000000;
	*PER_INT_MSK_REG  = 0x00000000;
	*CIC_STS_REG      = 0xFFFFFFFF;
	*PER_INT_STS_REG  = 0xFFFFFFFF;

#if defined(CONFIG_PMC_MSP7120_GW) || \
    defined(CONFIG_PMC_MSP7120_EVAL)
	/*
	 * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
	 * These inputs map to EXT_INT_POL[6:4] inside the CIC.
	 * They are to be active low, level sensitive.
	 */
	*CIC_EXT_CFG_REG &= 0xFFFF8F8F;
#endif

	/* initialize all the IRQ descriptors */
	for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++)
		set_irq_chip_and_handler(i, &msp_cic_irq_controller,
					 handle_level_irq);
}

static int __devexit ezx_pcap_remove(struct spi_device *spi)
{
	struct pcap_chip *pcap = dev_get_drvdata(&spi->dev);
	struct pcap_platform_data *pdata = spi->dev.platform_data;
	int i, adc_irq;

	/* remove all registered subdevs */
	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);

	/* cleanup ADC */
	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
				PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
	free_irq(adc_irq, pcap);
	mutex_lock(&pcap->adc_mutex);
	for (i = 0; i < PCAP_ADC_MAXQ; i++)
		kfree(pcap->adc_queue[i]);
	mutex_unlock(&pcap->adc_mutex);

	/* cleanup irqchip */
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
		set_irq_chip_and_handler(i, NULL, NULL);

	destroy_workqueue(pcap->workqueue);

	kfree(pcap);

	return 0;
}

static void __init ar71xx_misc_irq_init(void)
{
	void __iomem *base = ar71xx_reset_base;
	int i;

	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);

	switch (ar71xx_soc) {
	case AR71XX_SOC_AR7240:
	case AR71XX_SOC_AR7241:
	case AR71XX_SOC_AR7242:
	case AR71XX_SOC_AR9330:
	case AR71XX_SOC_AR9331:
	case AR71XX_SOC_AR9341:
	case AR71XX_SOC_AR9342:
	case AR71XX_SOC_AR9344:
		ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
		break;
	default:
		ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
		break;
	}

	for (i = AR71XX_MISC_IRQ_BASE;
	     i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
		set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
					 handle_level_irq);

	setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
}

void systemasic_irq_init(void)
{
	int i, nid = cpu_to_node(boot_cpu_data);

	/* Assign all virtual IRQs to the System ASIC int. handler */
	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
		unsigned int irq;

		irq = create_irq_nr(i, nid);
		if (unlikely(irq == 0)) {
			pr_err("%s: failed hooking irq %d for systemasic\n",
			       __func__, i);
			return;
		}

		if (unlikely(irq != i)) {
			pr_err("%s: got irq %d but wanted %d, bailing.\n",
			       __func__, irq, i);
			destroy_irq(irq);
			return;
		}

		set_irq_chip_and_handler(i, &systemasic_int,
					 handle_level_irq);
	}
}

void __init arch_init_irq(void)
{
	int i;

	switch (mips_machtype) {
	case MACH_LASAT_100:
		lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
		lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
		lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
		get_int_status = get_int_status_100;
		*lasat_int_mask = 0;
		break;
	case MACH_LASAT_200:
		lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
		lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
		lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
		get_int_status = get_int_status_200;
		*lasat_int_mask &= 0xffff;
		break;
	default:
		panic("arch_init_irq: mips_machtype incorrect");
	}

	for (i = 0; i <= LASATINT_END; i++)
		set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
}

void cpci_irq_init(void)
{
	int i;

	for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
		set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
}

int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
	struct msi_msg	msg;
	unsigned long	dest_phys_id;
	int	irq, vector;
	cpumask_t mask;

	irq = create_irq();
	if (irq < 0)
		return irq;

	set_irq_msi(irq, desc);
	cpus_and(mask, irq_to_domain(irq), cpu_online_map);
	dest_phys_id = cpu_physical_id(first_cpu(mask));
	vector = irq_to_vector(irq);

	msg.address_hi = 0;
	msg.address_lo =
		MSI_ADDR_HEADER |
		MSI_ADDR_DESTMODE_PHYS |
		MSI_ADDR_REDIRECTION_CPU |
		MSI_ADDR_DESTID_CPU(dest_phys_id);

	msg.data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		MSI_DATA_DELIVERY_FIXED |
		MSI_DATA_VECTOR(vector);

	write_msi_msg(irq, &msg);
	set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);

	return 0;
}

static void __init ilc_demux_init(struct platform_device *pdev)
{
	struct ilc *ilc = platform_get_drvdata(pdev);
	int irq;
	int i;

	/* Default all interrupts to active high. */
	for (i = 0, irq = ilc->first_irq; i < ilc->inputs_num; i++, irq++) {
		ILC_SET_TRIGMODE(ilc->base, i, ILC_TRIGGERMODE_HIGH);

		/* SIM: Should we do the masking etc in ilc_irq_demux and
		 * then change this to handle_simple_irq? */
		set_irq_chip_and_handler_name(irq, &ilc_chip,
				handle_level_irq, ilc->name);
		set_irq_chip_data(irq, ilc);
	}

	i = 0;
	irq = platform_get_irq(pdev, i++);
	while (irq >= 0) {
		set_irq_chip_and_handler(irq, &dummy_irq_chip, ilc_irq_demux);
		set_irq_data(irq, ilc);
		irq = platform_get_irq(pdev, i++);
	}

	return;
}

void __init arch_init_irq(void)
{
    int i;

       for (i = MSTAR_INT_BASE; i <= (OBERONINT_END+MSTAR_INT_BASE); i++) {
            if ( i <64+MSTAR_INT_BASE)
                set_irq_chip_and_handler(i, &oberon_irq_type, handle_level_irq);
            else
                set_irq_chip_and_handler(i, &oberon_irq_type, handle_level_irq);
       }
       set_irq_chip_and_handler(0, &oberon_fiq_type, handle_level_irq);
       set_irq_chip_and_handler(1, &oberon_fiq_type, handle_level_irq);
	//disable all
	Oberon_DisableInterrupt(E_IRQ_FIQ_ALL);

       mips_cpu_irq_init();
}

static int
cpld_pic_host_map(struct irq_host *h, unsigned int virq,
			     irq_hw_number_t hw)
{
	irq_to_desc(virq)->status |= IRQ_LEVEL;
	set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq);
	return 0;
}

static int flipper_pic_map(struct irq_host *h, unsigned int virq,
			   irq_hw_number_t hwirq)
{
	set_irq_chip_data(virq, h->host_data);
	irq_to_desc(virq)->status |= IRQ_LEVEL;
	set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
	return 0;
}