static void __init mpic_init_IRQ(void)
{
	struct device_node *dn;
	struct mpic *mpic;
	unsigned int virq;

	for (dn = NULL;
	     (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
		if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
			continue;

		/* The MPIC driver will get everything it needs from the
		 * device-tree, just pass 0 to all arguments
		 */
		mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC     ");
		if (mpic == NULL)
			continue;
		mpic_init(mpic);

		virq = irq_of_parse_and_map(dn, 0);
		if (virq == NO_IRQ)
			continue;

		printk(KERN_INFO "%s : hooking up to IRQ %d\n",
		       dn->full_name, virq);
		set_irq_data(virq, mpic);
		set_irq_chained_handler(virq, cell_mpic_cascade);
	}
}

int sapphire_init_gpio(void)
{
	int i;
	if (!machine_is_sapphire())
		return 0;

	DBG("%d,%d\r\n",SAPPHIRE_INT_START, SAPPHIRE_INT_END);
	DBG("NR_MSM_IRQS=%d, NR_GPIO_IRQS=%d\r\n", NR_MSM_IRQS, NR_GPIO_IRQS);
	for(i = SAPPHIRE_INT_START; i <= SAPPHIRE_INT_END; i++) {
		set_irq_chip(i, &sapphire_gpio_irq_chip);
		set_irq_handler(i, handle_edge_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	register_gpio_chip(&sapphire_gpio_chip);
	register_gpio_chip(&sapphire_h2w_gpio_chip);

	/*setup CPLD INT connecting to SOC's gpio 17 */
	set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
	set_irq_chained_handler(MSM_GPIO_TO_INT(17), sapphire_gpio_irq_handler);
	set_irq_wake(MSM_GPIO_TO_INT(17), 1);

	if(sysdev_class_register(&sapphire_sysdev_class) == 0)
		sysdev_register(&sapphire_irq_device);

	return 0;
}

void __init tx4927_irq_init(void)
{
	mips_cpu_irq_init();
	txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
	set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
				handle_simple_irq);
}

void __init iq80310_init_irq(void)
{
	volatile char *mask = (volatile char *)IQ80310_INT_MASK;
	unsigned int i;

	iop310_init_irq();

	/*
	 * Setup PIRSR to route PCI interrupts into xs80200
	 */
	*IOP310_PIRSR = 0xff;

	/*
	 * Setup the IRQs in the FE820000/FE860000 registers
	 */
	for (i = IQ80310_IRQ_OFS; i <= IRQ_IQ80310_INTD; i++) {
		set_irq_chip(i, &iq80310_irq_chip);
		set_irq_handler(i, do_level_IRQ);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	/*
	 * Setup the PCI IRQs
	 */
	for (i = IRQ_IQ80310_INTA; i < IRQ_IQ80310_INTC; i++) {
		set_irq_chip(i, &ext_chip);
		set_irq_handler(i, do_level_IRQ);
		set_irq_flags(i, IRQF_VALID);
	}

	*mask = 0xff;  /* mask all sources */

	set_irq_chained_handler(IRQ_XS80200_EXTIRQ,
				&iq80310_cpld_irq_handler);
}

void __init lh7a40x_init_board_irq (void)
{
    int irq;

    for (irq = IRQ_KEV7A400_CPLD;
         irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
        set_irq_chip (irq, &kev7a400_cpld_chip);
        set_irq_handler (irq, handle_edge_irq);
        set_irq_flags (irq, IRQF_VALID);
    }
    set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);

        /* Clear all CPLD interrupts */
    CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */

    GPIO_GPIOINTEN = 0;        /* Disable all GPIO interrupts */
    barrier();

#if 0
    GPIO_INTTYPE1
        = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
    GPIO_INTTYPE2 = 0;        /* Falling edge & low-level */
    GPIO_GPIOFEOI = 0xff;        /* Clear all GPIO interrupts */
    GPIO_GPIOINTEN = 0xff;        /* Enable all GPIO interrupts */

    init_FIQ();
#endif
}

void __init versatile_init_irq(void)
{
	unsigned int i;

	vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);

	set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);

	/* Do second interrupt controller */
	writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);

	for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
		if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
			set_irq_chip(i, &sic_chip);
			set_irq_handler(i, do_level_IRQ);
			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
		}
	}

	/*
	 * Interrupts on secondary controller from 0 to 8 are routed to
	 * source 31 on PIC.
	 * Interrupts from 21 to 31 are routed directly to the VIC on
	 * the corresponding number on primary controller. This is controlled
	 * by setting PIC_ENABLEx.
	 */
	writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
}

/*
 * Initialisation of PIC, this should be called in BSP
 */
void __init gef_pic_init(struct device_node *np)
{
    unsigned long flags;

    /* Map the devices registers into memory */
    gef_pic_irq_reg_base = of_iomap(np, 0);

    spin_lock_irqsave(&gef_pic_lock, flags);

    /* Initialise everything as masked. */
    out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
    out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);

    out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
    out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);

    spin_unlock_irqrestore(&gef_pic_lock, flags);

    /* Map controller */
    gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
    if (gef_pic_cascade_irq == NO_IRQ) {
        printk(KERN_ERR "SBC610: failed to map cascade interrupt");
        return;
    }

    /* Setup an irq_host structure */
    gef_pic_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
                                      GEF_PIC_NUM_IRQS,
                                      &gef_pic_host_ops, NO_IRQ);
    if (gef_pic_irq_host == NULL)
        return;

    /* Chain with parent controller */
    set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
}

/*
 * We only do anything if we are the master NPU on the board.
 * The slave NPU only has the ethernet chip going directly to
 * the PCIB interrupt input.
 */
void __init ixdp2x01_init_irq(void)
{
	int irq = 0;

	/* initialize chip specific interrupts */
	ixp2000_init_irq();

	if (machine_is_ixdp2401())
		valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
	else
		valid_irq_mask = IXDP2801_VALID_IRQ_MASK;

	/* Mask all interrupts from CPLD, disable simulation */
	ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
	ixp2000_reg_write(IXDP2X01_INT_SIM_REG, 0);

	for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
		if (irq & valid_irq_mask) {
			set_irq_chip(irq, &ixdp2x01_irq_chip);
			set_irq_handler(irq, do_level_IRQ);
			set_irq_flags(irq, IRQF_VALID);
		} else {
			set_irq_flags(irq, 0);
		}
	}

	/* Hook into PCI interrupts */
	set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x01_irq_handler);
}

static void __init xilinx_i8259_setup_cascade(void)
{
	struct device_node *cascade_node;
	int cascade_irq;

	/* Initialize i8259 controller */
	cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
	if (!cascade_node)
		return;

	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
	if (!cascade_irq) {
		pr_err("virtex_ml510: Failed to map cascade interrupt\n");
		goto out;
	}

	i8259_init(cascade_node, 0);
	set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);

	/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
	/* This looks like a dirty hack to me --gcl */
	outb(0xc0, 0x4d0);
	outb(0xc0, 0x4d1);

 out:
	of_node_put(cascade_node);
}

static int __init _mxc_expio_init(void)
{
	int i;

	initialized = 1;

	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
	/*
	 * Configure INT line as GPIO input
	 */
	mxc_request_iomux(MX31_PIN_GPIO1_4, OUTPUTCONFIG_GPIO,
			  INPUTCONFIG_GPIO);
	mxc_set_gpio_direction(MX31_PIN_GPIO1_4, 1);

	/* disable the interrupt and clear the status */
	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQT_HIGH);
	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);

	return 0;
}

static int s3c2412_irq_add(struct sys_device *sysdev)
{
	unsigned int irqno;

	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
		set_irq_chip(irqno, &s3c2412_irq_eint0t4);
		set_irq_handler(irqno, handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	/* add demux support for CF/SDI */

	set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);

	for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
		set_irq_chip(irqno, &s3c2412_irq_cfsdi);
		set_irq_handler(irqno, handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	/* change RTC IRQ's set wake method */

	s3c2412_irq_rtc_chip = s3c_irq_chip;
	s3c2412_irq_rtc_chip.set_wake = s3c2412_irq_rtc_wake;

	set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);

	return 0;
}

/* call this from board-specific init_irq */
void __init at91_gpio_irq_setup(unsigned banks)
{
	unsigned	pioc, pin, id;

	if (banks > 4)
		banks = 4;
	for (pioc = 0, pin = PIN_BASE, id = AT91C_ID_PIOA;
			pioc < banks;
			pioc++, id++) {
		struct pio_controller __iomem	*controller;
		unsigned			i;

		controller = (void __force __iomem *) pio_virt[pioc];
		__raw_writel(~0, &controller->idr);

		set_irq_data(id, (void *) pin);
		set_irq_chipdata(id, (void __force *) controller);

		for (i = 0; i < 32; i++, pin++) {
			set_irq_chip(pin, &gpio_irqchip);
			set_irq_handler(pin, do_simple_IRQ);
			set_irq_flags(pin, IRQF_VALID);
		}

		set_irq_chained_handler(id, gpio_irq_handler);

		/* enable the PIO peripheral clock */
		AT91_SYS->PMC_PCER = 1 << id;
	}
	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
}

static int __devinit neponset_probe(struct platform_device *dev)
{
	sa1100_register_uart_fns(&neponset_port_fns);

	/*
	 * Install handler for GPIO25.
	 */
	set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
	set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler);

	/*
	 * We would set IRQ_GPIO25 to be a wake-up IRQ, but
	 * unfortunately something on the Neponset activates
	 * this IRQ on sleep (ethernet?)
	 */
#if 0
	enable_irq_wake(IRQ_GPIO25);
#endif

	/*
	 * Setup other Neponset IRQs.  SA1111 will be done by the
	 * generic SA1111 code.
	 */
	set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
	set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
	set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
	set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);

	/*
	 * Disable GPIO 0/1 drivers so the buttons work on the module.
	 */
	NCR_0 = NCR_GP01_OFF;

	return 0;
}

void __init ixp23xx_init_irq(void)
{
    int irq;

    /* Route everything to IRQ */
    *IXP23XX_INTR_SEL1 = 0x0;
    *IXP23XX_INTR_SEL2 = 0x0;
    *IXP23XX_INTR_SEL3 = 0x0;
    *IXP23XX_INTR_SEL4 = 0x0;

    /* Mask all sources */
    *IXP23XX_INTR_EN1 = 0x0;
    *IXP23XX_INTR_EN2 = 0x0;
    *IXP23XX_INTR_EN3 = 0x0;
    *IXP23XX_INTR_EN4 = 0x0;

    /*
     * Configure all IRQs for level-sensitive operation
     */
    for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
        ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
    }

    for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
        set_irq_chip(irq, &ixp23xx_pci_irq_chip);
        set_irq_handler(irq, handle_level_irq);
        set_irq_flags(irq, IRQF_VALID);
    }

    set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
}

static __init int bast_irq_init(void)
{
	unsigned int i;

	if (machine_is_bast()) {
		printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");

		/* zap all the IRQs */

		__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);

		set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux);

		/* register our IRQs */

		for (i = 0; i < 4; i++) {
			unsigned int irqno = bast_pc104_irqs[i];

			set_irq_chip(irqno, &bast_pc104_chip);
			set_irq_handler(irqno, handle_level_irq);
			set_irq_flags(irqno, IRQF_VALID);
		}
	}

	return 0;
}

void __init ts4800_init_mux_irq(void)
{
   int n;
   volatile unsigned long x;
   volatile unsigned long *iomuxregs = (volatile unsigned long *)(AIPS1_BASE_ADDR_VIRT + 0x000A8000);
   gpioregs = (volatile unsigned long *)(AIPS1_BASE_ADDR_VIRT + 0x00088000);

   FPGA_REG(FPGA_IRQ_MASK_OFFSET) = 0xFFFF;  /* mask all */

    /*
    * On the TS-4800, the FPGA interrupt is connected to EIM_D27 on
    * the MX515. This pin must be configured as a GPIO pin, by writing
    * 001b to the MUX_MODE bits of the IOMUXC_SW_MUX_CTL_PAD_EIM_D27
    * register.  Doing so makes this pin EIM_GPIO2_9.
    */
   iomuxregs[0x88 / 4] = 1;

   gpioregs[0x18 / 4] = (1<<9);              // clr status for irq 169

   for(n=272; n < 280; n++)   {
      set_irq_chip(n, &muxed_irq_chip);
      set_irq_handler(n, handle_simple_irq);
      set_irq_flags(n, IRQF_VALID);
   }

   /* Install mux handler on GPIO2_9, which is IRQ #169 */
   set_irq_chained_handler(169, mux_irq_handler);

}

static int __init syncpt_init_irq(void)
{
	void __iomem *sync_regs;
	unsigned int i;
	int irq;

	sync_regs = ioremap(TEGRA_HOST1X_BASE + HOST1X_SYNC_OFFSET,
			HOST1X_SYNC_SIZE);
	BUG_ON(!sync_regs);

	writel(0xffffffffUL,
		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
	writel(0xffffffffUL,
		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);

	for (i = 0; i < INT_SYNCPT_THRESH_NR; i++) {
		irq = INT_SYNCPT_THRESH_BASE + i;
		set_irq_chip(irq, &syncpt_thresh_irq);
		set_irq_chip_data(irq, sync_regs);
		set_irq_handler(irq, handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
	if (set_irq_data(INT_HOST1X_MPCORE_SYNCPT, sync_regs))
		BUG();
	set_irq_chained_handler(INT_HOST1X_MPCORE_SYNCPT,
				syncpt_thresh_cascade);

	return 0;
}

void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
{
    if (gic_nr >= MAX_GIC_NR)
        BUG();
    if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
        BUG();
    set_irq_chained_handler(irq, gic_handle_cascade_irq);
}

int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
{
	int i, j;

	/* save for local usage */
	mxc_gpio_ports = port;
	gpio_table_size = cnt;

	printk(KERN_INFO "MXC GPIO hardware\n");

	for (i = 0; i < cnt; i++) {
		/* disable the interrupt and clear the status */
		__raw_writel(0, port[i].base + GPIO_IMR);
		__raw_writel(~0, port[i].base + GPIO_ISR);
		for (j = port[i].virtual_irq_start;
			j < port[i].virtual_irq_start + 32; j++) {
			set_irq_chip(j, &gpio_irq_chip);
			set_irq_handler(j, handle_edge_irq);
			set_irq_flags(j, IRQF_VALID);
		}

		/* register gpio chip */
		port[i].chip.direction_input = mxc_gpio_direction_input;
		port[i].chip.direction_output = mxc_gpio_direction_output;
		port[i].chip.get = mxc_gpio_get;
		port[i].chip.set = mxc_gpio_set;
		port[i].chip.base = i * 32;
		port[i].chip.ngpio = 32;

		/* its a serious configuration bug when it fails */
		BUG_ON( gpiochip_add(&port[i].chip) < 0 );

#ifdef CONFIG_ARCH_MX3
		/* setup one handler for each entry */
		set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
		set_irq_data(port[i].irq, &port[i]);
#endif
	}

#ifdef CONFIG_ARCH_MX2
	/* setup one handler for all GPIO interrupts */
	set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
	set_irq_data(port[0].irq, port);
#endif
	return 0;
}

int __init s3c64xx_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
		set_irq_chip(irq, &s3c_irq_eint);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
	set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
	set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
	set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);

	return 0;
}