/*
 * Initialize the rtInf, rtMinusInf, and rtNaN needed by the
 * generated code. NaN is initialized as non-signaling. Assumes IEEE.
 */
void rt_InitInfAndNaN(size_t realSize)
{
  (void) (realSize);
  rtNaN = rtGetNaN();
  rtNaNF = rtGetNaNF();
  rtInf = rtGetInf();
  rtInfF = rtGetInfF();
  rtMinusInf = rtGetMinusInf();
  rtMinusInfF = rtGetMinusInfF();
}

infF . wordL . wordLreal ; } real_T rtGetMinusInf ( void ) { size_t
bitsPerReal = sizeof ( real_T ) * ( NumBitsPerChar ) ; real_T minf = 0.0 ; if
( bitsPerReal == 32U ) { minf = rtGetMinusInfF ( ) ; } else { uint16_T one =
1U ; enum { LittleEndian , BigEndian } machByteOrder = ( * ( ( uint8_T * ) &
one ) == 1U ) ? LittleEndian : BigEndian ; switch ( machByteOrder ) { case
LittleEndian : { union { LittleEndianIEEEDouble bitVal ; real_T fltVal ; }
tmpVal ; tmpVal . bitVal . words . wordH = 0xFFF00000U ; tmpVal . bitVal .
words . wordL = 0x00000000U ; minf = tmpVal . fltVal ; break ; } case
BigEndian : { union { BigEndianIEEEDouble bitVal ; real_T fltVal ; } tmpVal ;
tmpVal . bitVal . words . wordH = 0xFFF00000U ; tmpVal . bitVal . words .
wordL = 0x00000000U ; minf = tmpVal . fltVal ; break ; } } } return minf ; }

/*
 * Initialize rtMinusInf needed by the generated code.
 * Inf is initialized as non-signaling. Assumes IEEE.
 */
real_T rtGetMinusInf(void)
{
  size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
  real_T minf = 0.0;
  if (bitsPerReal == 32U) {
    minf = rtGetMinusInfF();
  } else {
    union {
      LittleEndianIEEEDouble bitVal;
      real_T fltVal;
    } tmpVal;

    tmpVal.bitVal.words.wordH = 0xFFF00000U;
    tmpVal.bitVal.words.wordL = 0x00000000U;
    minf = tmpVal.fltVal;
  }

  return minf;
}

rtMinusInfF ; real32_T rtNaNF ; void rt_InitInfAndNaN ( size_t realSize ) { (
void ) ( realSize ) ; rtNaN = rtGetNaN ( ) ; rtNaNF = rtGetNaNF ( ) ; rtInf =
rtGetInf ( ) ; rtInfF = rtGetInfF ( ) ; rtMinusInf = rtGetMinusInf ( ) ;
rtMinusInfF = rtGetMinusInfF ( ) ; } boolean_T rtIsInf ( real_T value ) {