int efm32_rtc_cancelalarm(void)
{
  irqstate_t flags;
  int ret = -ENODATA;

  if (g_alarmcb != NULL)
    {
      /* Cancel the global callback function */

      g_alarmcb = NULL;

      /* Unset the alarm */

      flags = irqsave();
      stm32_rtc_beginwr();
      putreg16(0xffff, STM32_RTC_ALRH);
      putreg16(0xffff, STM32_RTC_ALRL);
      stm32_rtc_endwr();
      irqrestore(flags);

      ret = OK;
    }

  return ret;
}

void up_irqinitialize(void)
{
  /* Prepare hardware */

  calypso_exceptions_install();
  current_regs = NULL;

  /* Switch to internal ROM */

  calypso_bootrom(1);

  /* Set default priorities */

  set_default_priorities();

  /* Mask all interrupts off */

  putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
  putreg16(0xffff, IRQ_REG(MASK_IT_REG2));

  /* clear all pending interrupts */
  putreg16(0, IRQ_REG(IT_REG1));
  putreg16(0, IRQ_REG(IT_REG2));

  /* Enable interrupts globally to the ARM core */

#ifndef CONFIG_SUPPRESS_INTERRUPTS
  irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}

void up_ack_irq(int irq)
{
  /* Acknowlege the interrupt by setting the corresponding bit in the
   * IRQ status register.
   */

  if (irq < 16)
    {
      /* Set the associated status bit to clear the interrupt */

      putreg16((1 << irq), DM320_INTC_IRQ0);
    }
  else if (irq < 32)
    {
      /* Set the associated status bit to clear the interrupt  */

      putreg16((1 << (irq-16)), DM320_INTC_IRQ1);
    }
  else
    {
      /* Set the associated status bit to clear the interrupt */

      putreg16((1 << (irq-32)), DM320_INTC_IRQ2);
    }
}

void wdog_enable(int on)
{
	if (!on) {
		putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
		putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
	}
}

static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power)
{
  DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER);

  /* Set new power level */

  if (power > 0)
    {
      uint32_t duty;

      /* Calculate the new backlight duty.  It is a fraction of the timer
       * period based on the ration of the current power setting to the
       * maximum power setting.
       */

      duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / CONFIG_LCD_MAXPOWER;
      if (duty >= LCD_BL_TIMER_PERIOD)
        {
          duty = LCD_BL_TIMER_PERIOD - 1;
        }

      putreg16((uint16_t)duty, STM32_TIM3_CCR2);
    }
  else
    {
      putreg16((uint16_t)0, STM32_TIM3_CCR2);
    }
}

static void lcd_wrdata(uint8_t data)
{
  /* Make sure that the LCD is available */

  lcd_waitbusy();

  /* Select DB0-15 as outputs (only DB-0-7 are actually used) */

  putreg16(0, PIC32MX_IOPORTE_TRIS);

  /* Set up to write the data */

  pic32mx_gpiowrite(GPIO_LCD_RS, true);    /* Select data */
  pic32mx_gpiowrite(GPIO_LCD_RW, false);   /* Select write */
  lcd_shortdelay(2);

  pic32mx_gpiowrite(GPIO_LCD_E, true);     /* Enable transfer */
  lcd_shortdelay(1);

  /* Write the data to the LCD */

  putreg16(data, PIC32MX_IOPORTE_PORT);    /* Write the data */
  lcd_shortdelay(1);
  pic32mx_gpiowrite(GPIO_LCD_E, false);
}

void spi_init(void)
{
  putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
           SPI_REG(REG_SET1));

  putreg16(0x0001, SPI_REG(REG_SET2));
}

void up_enable_irq(int irq)
{
  /* Enable the interrupt by setting the corresponding bit in
   * the IRQ enable register.
   */

  if (irq < 16)
    {
      /* IRQs0-15 are controlled by the IRQ0 enable register
       * Set the associated bit to enable the interrupt
       */

      putreg16((getreg16(DM320_INTC_EINT0) | (1 << irq)), DM320_INTC_EINT0);
    }
  else if (irq < 32)
    {
      /* IRQs16-31 are controlled by the IRQ1 enable register
       * Set the associated bit to enable the interrupt
       */

      putreg16((getreg16(DM320_INTC_EINT1) | (1 << (irq-16))), DM320_INTC_EINT1);
    }
  else
    {
      /* IRQs32- are controlled by the IRQ2 enable register
       * Set the associated bit to enable the interrupt
       */

      putreg16((getreg16(DM320_INTC_EINT2) | (1 << (irq-32))), DM320_INTC_EINT2);
    }
}

int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
{
  uint16_t tmp = 0;

  if (bitlen <= 0 || bitlen > 16)
      return -1;

  if (cs < 0 || cs > 4)
      return -1;

  /* FIXME uwire_init always selects CS0 for now */

  dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);

  /* select the chip */

  putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);

  if (dout)
    {
      if (bitlen <= 8)
          tmp = *(uint8_t *)dout;
      else if (bitlen <= 16)
          tmp = *(uint16_t *)dout;

      tmp <<= 16 - bitlen; /* align to MSB */
      putreg16(tmp, UWIRE_REG(REG_DATA));
      dbg(", data_out=0x%04hx", tmp);
    }

  tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
        (din  ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
         UWIRE_CSR_START;
  putreg16(tmp, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);

  if (din)
    {
      _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);

      tmp = getreg16(UWIRE_REG(REG_DATA));
      dbg(", data_in=0x%08x", tmp);

      if (bitlen <= 8)
          *(uint8_t *)din = tmp & 0xff;
      else if (bitlen <= 16)
          *(uint16_t *)din = tmp & 0xffff;
    }

  /* unselect the chip */

  putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);

  dbg(")\n");

  return 0;
}

void wdog_reset(void)
{
	// enable watchdog
	putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
	// force expiration
	putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
	putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
}

void uwire_init(void)
{
  putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));

  /* FIXME only init CS0 for now */

  putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
           UWIRE_REG(UWIRE_CSn_REG(0)));
  putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);
}

void wdog_reset(void)
{
  /* Enable watchdog */

  putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));

  /* Force expiration */

  putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
  putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
}

static void dm320_disable(void)
{
  /* Disable all planes */

  gvdbg("Inactivate OSD:\n");

  putreg16(0, DM320_OSD_OSDWIN0MD); /* Win0 mode = 0 (1:active) */
  putreg16(0, DM320_OSD_OSDWIN1MD); /* Win1 mode = 0 (1:active) */
  putreg16(0, DM320_OSD_RECTCUR);   /* Rectangular cursor mode = 0 (1:active) */

  gvdbg("DM320_OSD_OSDWIN0MD:   %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
  gvdbg("DM320_OSD_OSDWIN1MD:   %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
  gvdbg("DM320_OSD_RECTCUR:     %04x\n", getreg16(DM320_OSD_RECTCUR));
}

void up_timerinit(void)
{
  uint32_t reload;
 
  up_disable_irq(Z8_IRQ_SYSTIMER);

  /* Write to the timer control register to disable the timer, configure
   * the timer for continuous mode, and set up the pre-scale value for
   * divide by 4.
   */

  putreg8((Z8_TIMERCTL_DIV4|Z8_TIMERCTL_CONT), T0CTL);

  /* Write to the timer high and low byte registers to set a starting
   * count value (this effects only the first pass in continuous mode)
   */

  putreg16(0x0001, T0);

  /* Write to the timer reload register to set the reload value.
   *
   * In continuous mode:
   *
   *   timer_period = reload_value x prescale / system_clock_frequency
   * or
   *   reload_value = (timer_period * system_clock_frequency) / prescale
   *
   * For system_clock_frequency=18.432MHz, timer_period=10mS, and prescale=4,
   * then reload_value=46,080 - OR:
   *
   *   reload_value = system_clock_frequency / 400
   */

   reload = get_freq() / 400;
   putreg16((uint16_t)reload, T0R);

  /* Write to the timer control register to enable the timer and to
   * initiate counting
   */

  putreg8((getreg8(T0CTL)|Z8_TIMERCTL_TEN), T0CTL);

  /* Set the timer priority */

  /* Attach and enable the timer interrupt (leaving at priority 0 */

  irq_attach(Z8_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
  up_enable_irq(Z8_IRQ_SYSTIMER);
}

void sercom_slowclk_configure(int gclkgen)
{
  static bool configured = false;
  uint16_t regval;

  /* Since GCLK_SERCOM_SLOW is shard amongst all SERCOM modules, it should
   * only be configured one time.
   */

  if (!configured)
    {
      /* Set up the SERCOM_GCLK_ID_SLOW clock */

      regval = (SERCOM_GCLK_ID_SLOW << GCLK_CLKCTRL_ID_SHIFT);

      /* Select and disable the SERCOM_GCLK_ID_SLOW generic clock */

      putreg16(regval, SAM_GCLK_CLKCTRL);

      /* Wait for clock to become disabled */

      while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);

      /* Select the SERCOM_GCLK_ID_SLOW clock source generator */

      regval |= (uint16_t)gclkgen << GCLK_CLKCTRL_GEN_SHIFT;

      /* Write the new configuration */

      putreg16(regval, SAM_GCLK_CLKCTRL);

      /* Enable the GCLK_SERCOM_SLOW generic clock and lock further
       * writes to this GCLK.  When this bit is written, it will lock
       * further writes to the generic clock pointed by the CLKCTRL.ID. The
       * generic clock generator pointed by CLKCTRL.GEN and the GENDIV.DIV
       * will also be locked.
       *
       * We lock the SERCOM slow clock because it is common to all SERCOM modules
       * and, once set, should not be changed again.
       */

      regval |= (/* GCLK_CLKCTRL_WRTLOCK | */ GCLK_CLKCTRL_CLKEN);
      putreg16(regval, SAM_GCLK_CLKCTRL);

      /* Now we are configured */

      configured = true;
    }
}

static int dm320_putcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *cmap)
{
  irqstate_t flags;
  uint16_t regval;
  uint8_t y;
  uint8_t u;
  uint8_t v;
  int len
  int i;

#ifdef CONFIG_DEBUG
  if (!vtable || !cmap || !cmap->read || !cmap->green || !cmap->blue)
    {
      return -EINVAL;
    }
#endif

  flags = enter_critical_section();
  for (i = cmap.first, len = 0; i < 256 && len < cmap.len, i++, len++)
    {
      /* Convert the RGB to YUV */

      nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v);

      /* Program the CLUT */

      while (getreg16(DM320_OSD_MISCCTL) & 0x8);
      putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB);
      putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR);
    }

  /* Select RAM clut */

#if !defined(CONFIG_DM320_OSD0_DISABLE) && !defined(CONFIG_DM320_OSD0_RGB16)
  regval = getreg16(DM320_OSD_OSDWIN0MD);
  regval |= 0x1000;
  putreg16(regval, DM320_OSD_OSDWIN0MD);
#endif

#if !defined(CONFIG_DM320_OSD1_DISABLE) && !defined(CONFIG_DM320_OSD1_RGB16)
  regval = getreg16(DM320_OSD_OSDWIN1MD);
  regval |= 0x1000;
  putreg16(regval, DM320_OSD_OSDWIN1MD);
#endif

  leave_critical_section(flags);
  return 0;
}

static void set_default_priorities(void)
{
  unsigned int i;

  for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++)
    {
      uint16_t val;
      uint8_t prio = default_irq_prio[i];

      if (prio > 31)
        {
          prio = 31;
        }

      val = getreg16(IRQ_REG(ILR_IRQ(i)));
      val &= ~(0x1f << 2);
      val |= prio << 2;

      /* Make edge mode default. Hopefully causes less trouble */

      val |= 0x02;

      putreg16(val, IRQ_REG(ILR_IRQ(i)));
    }
}

static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
    FAR uint8_t *ptr = (FAR uint8_t*)buffer;
    uint32_t rxpending = 0;

    /* While there is remaining to be sent (and no synchronization error has occurred) */

    spidbg("nwords: %d\n", nwords);
    while (nwords || rxpending)
    {
        /* Fill the transmit FIFO with 0xff...
         * Write 0xff to the data register while (1) the TX FIFO is
         * not full, (2) we have not exceeded the depth of the TX FIFO,
         * and (3) there are more bytes to be sent.
         */

        spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
        while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) &&
                (rxpending < LPC214X_SPI1_FIFOSZ) && nwords)
        {
            putreg16(0xff, LPC214X_SPI1_DR);
            nwords--;
            rxpending++;
        }

        /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */

        spivdbg("RX: rxpending: %d\n", rxpending);
        while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)
        {
            *ptr++ = (uint8_t)getreg16(LPC214X_SPI1_DR);
            rxpending--;
        }
    }
}

static int lcd_setpower(struct lcd_dev_s *dev, int power)
{
  uint16_t reg;

  if (g_lcddev.power == power) {
    return OK;
  }

  ginfo("power: %d\n", power);
  DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER);

  /* Set new power level */
  reg = getreg16(ASIC_CONF_REG);
  if (power)
    {
      reg = getreg16(ASIC_CONF_REG);
      /* LCD Set I/O(3) / SA0 to I/O(3) mode */
      reg &= ~( (1 << 12) | (1 << 10) | (1 << 7) | (1 << 1)) ;
      /* don't set function pins to I2C Mode, C155 uses UWire */
      /* TWL3025: Set SPI+RIF RX clock to rising edge */
      reg |= (1 << 13) | (1 << 14);
      putreg16(reg, ASIC_CONF_REG);

      /* LCD Set I/O(3) to output mode and enable C155 backlight (IO1) */
      /* FIXME: Put the display backlight control to backlight.c */
      reg = getreg16(IO_CNTL_REG);
      reg &= ~( (1 << 3) | (1 << 1));
      putreg16(reg, IO_CNTL_REG);

      /* LCD Set I/O(3) output low */
      reg = getreg16(ARMIO_LATCH_OUT);
      reg &= ~(1 << 3);
      reg |= (1 << 1);
      putreg16(reg, ARMIO_LATCH_OUT);
    }
    else
    {
      ginfo("powering LCD off...\n");
      /* Switch pin from PWL to LT */
      reg &= ~ASCONF_PWL_ENA;
      putreg8(reg, ASIC_CONF_REG);
      /* Disable pwl */
      putreg8(0x00, PWL_REG(PWL_CTRL));
    }
    return OK;
}

static void cs89x0_putreg(struct cs89x0_driver_s *cs89x0, int offset, uint16_t value)
{
#ifdef CONFIG_CS89x0_ALIGN16
  return putreg16(value, s89x0->cs_base + offset);
#else
  return (uint16_t)putreg32((uint32_t)value, s89x0->cs_base + offset);
#endif
}