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C++ pnp_write_config函数代码示例

原作者: [db:作者] 来自: [db:来源] 收藏 邀请

本文整理汇总了C++中pnp_write_config函数的典型用法代码示例。如果您正苦于以下问题：C++ pnp_write_config函数的具体用法？C++ pnp_write_config怎么用？C++ pnp_write_config使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。



在下文中一共展示了pnp_write_config函数的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。

示例1: f71869ad_multifunc_init

void f71869ad_multifunc_init(struct device *dev)
{
	const struct superio_fintek_f71869ad_config *conf = dev->chip_info;

	pnp_enter_conf_mode(dev);

	/* multi-func select reg1 */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
			conf->multi_function_register_1);

	/* multi-func select reg2 (CLK_TUNE_EN=0) */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
			conf->multi_function_register_2);

	/* multi-func select reg3 (CLK_TUNE_EN=0) */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
			conf->multi_function_register_3);

	/* multi-func select reg4 (CLK_TUNE_EN=0) */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
			conf->multi_function_register_4);

	/* multi-func select reg5 (CLK_TUNE_EN=0) */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG5,
			conf->multi_function_register_5);

	pnp_exit_conf_mode(dev);
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:28，代码来源:f71869ad_multifunc.c


示例2: sch4037_early_init

void sch4037_early_init(unsigned port)
{
	pnp_devfn_t dev;

	dev = PNP_DEV(port, SMSCSUPERIO_SP1);
	pnp_enter_conf_state(dev);

	/* Auto power management */
	pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
	pnp_write_config(dev, 0x23, 0);

	/* Enable SMSC UART 0 */
	dev = PNP_DEV(port, SMSCSUPERIO_SP1);
	pnp_set_logical_device(dev);
	pnp_set_enable(dev, 0);

	pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
	pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);

	/* Enabled High speed, disabled MIDI support. */
	pnp_write_config(dev, 0xF0, 0x02);
	pnp_set_enable(dev, 1);

	/* Enable keyboard */
	dev = PNP_DEV(port, SCH4037_KBC);
	pnp_set_logical_device(dev);
	pnp_set_enable(dev, 0);
	pnp_set_irq(dev, 0x70, 1);   /* IRQ 1 */
	pnp_set_irq(dev, 0x72, 12);   /* IRQ 12 */
	pnp_set_enable(dev, 1);

	pnp_exit_conf_state(dev);
}
开发者ID:canistation，项目名称:coreboot，代码行数:33，代码来源:sch4037_early_init.c


示例3: mainboard_config_superio

void mainboard_config_superio(void)
{
	const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
	const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
	const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
	const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2);

	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

	nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);

	/* Select HWM/LED functions instead of floppy functions. */
	pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
	pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);

	/* Power RAM in S3 and let the PCH handle power failure actions. */
	pnp_set_logical_device(ACPI_DEV);
	pnp_write_config(ACPI_DEV, 0xe4, 0x70);

	/*
	 * Don't know what's needed here, just set the same as the vendor
	 * firmware.
	 */
	pnp_set_logical_device(IR_DEV);
	pnp_write_config(IR_DEV, 0xf1, 0x5c);

	nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
}
开发者ID:canistation，项目名称:coreboot，代码行数:28，代码来源:romstage.c


示例4: f71808a_multifunc_init

void f71808a_multifunc_init(struct device *dev)
{
	const struct superio_fintek_f71808a_config *conf = dev->chip_info;

	pnp_enter_conf_mode(dev);

	/* multi-func select reg0 */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG0,
			conf->multi_function_register_0);

	/* multi-func select reg1 */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
			conf->multi_function_register_1);

	/* multi-func select reg2 */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
			conf->multi_function_register_2);

	/* multi-func select reg3 */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
			conf->multi_function_register_3);

	/* multi-func select reg4 */
	pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
			conf->multi_function_register_4);

	pnp_exit_conf_mode(dev);
}
开发者ID:canistation，项目名称:coreboot，代码行数:28，代码来源:f71808a_multifunc.c


示例5: lpc47n227_pnp_set_irq

void lpc47n227_pnp_set_irq(struct device *dev, u8 irq)
{
	u8 irq_config_register = 0, irq_config_mask = 0;
	u8 current_config, new_config;

	switch (dev->path.pnp.device) {
	case LPC47N227_PP:
		irq_config_register = 0x27;
		irq_config_mask = 0x0F;
		break;
	case LPC47N227_SP1:
		irq_config_register = 0x28;
		irq_config_mask = 0xF0;
		irq <<= 4;
		break;
	case LPC47N227_SP2:
		irq_config_register = 0x28;
		irq_config_mask = 0x0F;
		break;
	case LPC47N227_KBDC:
		break;
	default:
		BUG();
		return;
	}

	current_config = pnp_read_config(dev, irq_config_register);
	new_config = (current_config & ~irq_config_mask) | irq;
	pnp_write_config(dev, irq_config_register, new_config);
}
开发者ID:killbug2004，项目名称:coreboot，代码行数:30，代码来源:superio.c


示例6: lpc47n217_pnp_set_enable

static void lpc47n217_pnp_set_enable(device_t dev, int enable)
{
	u8 power_register = 0, power_mask = 0, current_power, new_power;

	switch(dev->path.pnp.device) {
	case LPC47N217_PP:
		power_register = 0x01;
		power_mask = 0x04;
		break;
	case LPC47N217_SP1:
		power_register = 0x02;
		power_mask = 0x08;
		break;
	case LPC47N217_SP2:
		power_register = 0x02;
		power_mask = 0x80;
		break;
	default:
		BUG();
		return;
	}

	current_power = pnp_read_config(dev, power_register);
	new_power = current_power & ~power_mask; /* Disable by default. */
	if (enable) {
		struct resource* ioport_resource;
		ioport_resource = find_resource(dev, PNP_IDX_IO0);
		lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
		new_power |= power_mask; /* Enable. */
	} else {
		lpc47n217_pnp_set_iobase(dev, 0);
	}
	pnp_write_config(dev, power_register, new_power);
}
开发者ID:bolyboly，项目名称:coreboot，代码行数:34，代码来源:superio.c


示例7: lpc47n217_pnp_set_irq

static void lpc47n217_pnp_set_irq(device_t dev, u8 irq)
{
	u8 irq_config_register = 0, irq_config_mask = 0;
	u8 current_config, new_config;

	switch(dev->path.pnp.device) {
	case LPC47N217_PP:
		irq_config_register = 0x27;
		irq_config_mask = 0x0F;
		break;
	case LPC47N217_SP1:
		irq_config_register = 0x28;
		irq_config_mask = 0xF0;
		irq <<= 4;
		break;
	case LPC47N217_SP2:
		irq_config_register = 0x28;
		irq_config_mask = 0x0F;
		break;
	default:
		BUG();
		return;
	}

	ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range? */

	current_config = pnp_read_config(dev, irq_config_register);
	new_config = (current_config & ~irq_config_mask) | irq;
	pnp_write_config(dev, irq_config_register, new_config);
}
开发者ID:bolyboly，项目名称:coreboot，代码行数:30，代码来源:superio.c


示例8: init

static void init(struct device *dev)
{
	u8 reg8;

	if (!dev->enabled)
		return;

	switch(dev->path.pnp.device) {
	case PC97307_KBCK:
		pnp_set_logical_device(dev);
		pnp_set_enable(dev, 0);		   /* Disable keyboard */
		pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
		pnp_set_enable(dev, 1);		   /* Enable keyboard. */
		pc_keyboard_init();
		break;
	case PC97307_FDC:
		/* Set up floppy in PS/2 mode. */
		outb(0x09, SIO_CONFIG_RA);
		reg8 = inb(SIO_CONFIG_RD);
		reg8 = (reg8 & 0x3F) | 0x40;
		outb(reg8, SIO_CONFIG_RD);
		outb(reg8, SIO_CONFIG_RD); /* Have to write twice to change! */
		break;
	default:
		break;
	}
}
开发者ID:kmalkki，项目名称:coreboot，代码行数:27，代码来源:superio.c


示例9: route_pins_to_uart

static void route_pins_to_uart(struct device *dev, bool to_uart)
{
    u8 reg;

    reg = pnp_read_config(dev, 0x1c);

    switch (dev->path.pnp.device) {
    case NCT5104D_SP3:
    case NCT5104D_GPIO0:
        /* Route pins 33 - 40. */
        if (to_uart)
            reg |= (1 << 3);
        else
            reg &= ~(1 << 3);
        break;
    case NCT5104D_SP4:
    case NCT5104D_GPIO1:
        /* Route pins 41 - 48. */
        if (to_uart)
            reg |= (1 << 2);
        else
            reg &= ~(1 << 2);
        break;
    default:
        break;
    }

    pnp_write_config(dev, 0x1c, reg);
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:29，代码来源:superio.c


示例10: enable_hwm_smbus

static void enable_hwm_smbus(device_t dev)
{
	/* Enable SensorBus register access. */
	u8 reg8;

	reg8 = pnp_read_config(dev, 0xf0);
	reg8 |= (1 << 1);
	pnp_write_config(dev, 0xf0, reg8);
}
开发者ID:bolyboly，项目名称:coreboot，代码行数:9，代码来源:superio.c


示例11: w83627dhg_enable_UR2

static void w83627dhg_enable_UR2(struct device *dev)
{
	u8 reg8;

	pnp_enter_conf_mode(dev);
	reg8 = pnp_read_config(dev, 0x2c);
	reg8 |= (0x3);
	pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B
	pnp_exit_conf_mode(dev);
}
开发者ID:canistation，项目名称:coreboot，代码行数:10，代码来源:superio.c


示例12: set_uart_clock_source

/*
 * Set the UART clock source.
 *
 * Possible UART clock source speeds are:
 *
 *   0 = 1.8462 MHz (default)
 *   1 = 2 MHz
 *   2 = 24 MHz
 *   3 = 14.769 MHz
 *
 * The faster clocks allow for BAUD rates up to 2mbits.
 *
 * Warning: The kernel will need to be adjusted since it assumes
 * a 1.8462 MHz clock.
 */
static void set_uart_clock_source(device_t dev, u8 uart_clock)
{
	u8 value;

	w83627uhg_enter_ext_func_mode(dev);
	pnp_set_logical_device(dev);
	value = pnp_read_config(dev, 0xf0);
	value &= ~0x03;
	value |= (uart_clock & 0x03);
	pnp_write_config(dev, 0xf0, value);
	w83627uhg_exit_ext_func_mode(dev);
}
开发者ID:kelsieflynn，项目名称:coreboot-1，代码行数:27，代码来源:superio.c


示例13: mainboard_set_e7520_pll

static void mainboard_set_e7520_pll(unsigned bits)
{
	uint16_t gpio_index;
	uint8_t data;
	device_t dev;

	/* currently only handle the Jarrell/PC87427 case */
	dev = PC87427_GPIO_DEV;


	pnp_set_logical_device(dev);
	gpio_index = pnp_read_iobase(dev, 0x60);

	/* select SIO GPIO port 4, pin 2 */
	pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
	/* set to push-pull, enable output */
	pnp_write_config(dev, PC87427_GPCFG1, 0x03);

	/* select SIO GPIO port 4, pin 4 */
	pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
	/* set to push-pull, enable output */
	pnp_write_config(dev, PC87427_GPCFG1, 0x03);

	/* set gpio 42,44 signal levels */
	data = inb(gpio_index + PC87427_GPDO_4);
	if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
		print_debug("set_pllsel: correct settings detected!\n");
		return; /* settings already configured */
	} else {
		outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
		/* reset */
		print_debug("set_pllsel: settings adjusted, now resetting...\n");
		// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
		// mch_reset();
		full_reset();
	}
	return;
}
开发者ID:XVilka，项目名称:coreboot，代码行数:38，代码来源:jarrell_fixups.c


示例14: sio_init

static void sio_init(void)
{
	u8 reg;

	pnp_enter_ext_func_mode(SERIAL_DEV);
	reg = pnp_read_config(SERIAL_DEV, 0x24);
	/* 4 Mbit flash */
	reg = (reg & ~0x30) | 0x20;
	/* We have 24MHz input. */
	reg &= ~0x40;
	/* enable MEMW#, so flash can be written */
	reg |= 0x08;
	pnp_write_config(SERIAL_DEV, 0x24, reg);
}
开发者ID:andy737，项目名称:firebrickRemote，代码行数:14，代码来源:romstage.c


示例15: init

static void init(device_t dev)
{
	struct superio_nsc_pc97317_config *conf;
	struct resource *res0, *res1;

	if (!dev->enabled) {
		return;
	}
	conf = dev->chip_info;
	switch(dev->path.pnp.device) {
	case PC97317_SP1:
		res0 = find_resource(dev, PNP_IDX_IO0);
		init_uart8250(res0->base, &conf->com1);
		break;

	case PC97317_SP2:
		res0 = find_resource(dev, PNP_IDX_IO0);
		init_uart8250(res0->base, &conf->com2);
		break;

	case PC97317_KBCK:
		/* Enable keyboard */
		pnp_set_logical_device(dev);
		pnp_set_enable(dev, 0); /* Disable keyboard */
		pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */
		pnp_set_enable(dev, 1); /* Enable keyboard */

		res0 = find_resource(dev, PNP_IDX_IO0);
		res1 = find_resource(dev, PNP_IDX_IO1);
		pc_keyboard_init(&conf->keyboard);
		break;

#if 0
	case PC97317_FDC:
	{
		unsigned reg;
		/* Set up floppy in PS/2 mode */
		outb(0x09, SIO_CONFIG_RA);
		reg = inb(SIO_CONFIG_RD);
		reg = (reg & 0x3F) | 0x40;
		outb(reg, SIO_CONFIG_RD);
		outb(reg, SIO_CONFIG_RD);       /* Have to write twice to change! */
		break;
	}
#endif
	default:
		break;
	}
}
开发者ID:kelsieflynn，项目名称:coreboot-1，代码行数:49，代码来源:superio.c


示例16: early_superio_config

static void early_superio_config(void)
{
	int timeout = 100000;
	pnp_devfn_t dev = PNP_DEV(0x2e, 3);

	pnp_write_config(dev, 0x29, 0x06);

	while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--)
		udelay(1000);

	/* Enable COM1 */
	pnp_set_logical_device(dev);
	pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
	pnp_set_enable(dev, 1);
}
开发者ID:siro20，项目名称:coreboot，代码行数:15，代码来源:romstage.c


示例17: init_acpi

static void init_acpi(device_t dev)
{
	u8 value = 0x20; /* TODO: 0x20 value here never used? */
	int power_on = 1;

	get_option(&power_on, "power_on_after_fail");
	pnp_enter_conf_mode(dev);
	pnp_set_logical_device(dev);
	value = pnp_read_config(dev, 0xe4);
	value &= ~(3 << 5);
	if (power_on)
		value |= (1 << 5);
	pnp_write_config(dev, 0xe4, value);
	pnp_exit_conf_mode(dev);
}
开发者ID:mytbk，项目名称:coreboot，代码行数:15，代码来源:superio.c


示例18: xbus_cfg

void xbus_cfg(pnp_devfn_t dev)
{
	u8 i;
	u16 xbus_index;

	pnp_set_logical_device(dev);
	/* Select proper BIOS size (4MB). */
	pnp_write_config(dev, PC87417_XMEMCNF2,
			 (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
	xbus_index = pnp_read_iobase(dev, 0x60);

	/* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
	for (i = 0; i <= 0xf; i++)
		outb((i << 4), xbus_index + PC87417_HAP0);
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:15，代码来源:early_init.c


示例19: set_irq_trigger_type

static void set_irq_trigger_type(struct device *dev, bool trig_level)
{
    u8 reg10, reg11, reg26;

    //Before accessing CR10 OR CR11 Bit 4 in CR26 must be set to 1
    reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
    reg26 |= CR26_LOCK_REG;
    pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);

    switch(dev->path.pnp.device) {
    //SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5
    case NCT5104D_SP1:
        reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
        if (trig_level)
            reg10 |= (1 << 5);
        else
            reg10 &= ~(1 << 5);
        pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
        break;
    //SP2 (UARTB) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 4
    case NCT5104D_SP2:
        reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
        if (trig_level)
            reg10 |= (1 << 4);
        else
            reg10 &= ~(1 << 4);
        pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
        break;
    //SP3 (UARTC) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 5
    case NCT5104D_SP3:
        reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
        if (trig_level)
            reg11 |= (1 << 5);
        else
            reg11 &= ~(1 << 5);
        pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
        break;
    //SP4 (UARTD) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 4
    case NCT5104D_SP4:
        reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
        if (trig_level)
            reg11 |= (1 << 4);
        else
            reg11 &= ~(1 << 4);
        pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
        break;
    default:
        break;
    }

    //Clear access control register
    reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
    reg26 &= ~CR26_LOCK_REG;
    pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:55，代码来源:superio.c


示例20: lpc47n217_pnp_set_drq

static void lpc47n217_pnp_set_drq(device_t dev, u8 drq)
{
	const u8 PP_DMA_MASK = 0x0F;
	const u8 PP_DMA_SELECTION_REGISTER = 0x26;
	u8 current_config, new_config;

	if (dev->path.pnp.device == LPC47N217_PP) {
		current_config = pnp_read_config(dev,
						 PP_DMA_SELECTION_REGISTER);
		ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range? */
		new_config = (current_config & ~PP_DMA_MASK) | drq;
		pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
	} else {
		BUG();
	}
}
开发者ID:bolyboly，项目名称:coreboot，代码行数:16，代码来源:superio.c



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