本文整理汇总了C++中pci_read_config32函数的典型用法代码示例。如果您正苦于以下问题：C++ pci_read_config32函数的具体用法？C++ pci_read_config32怎么用？C++ pci_read_config32使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了pci_read_config32函数的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: init_bootmode_straps
void init_bootmode_straps(void)
{
#ifdef __PRE_RAM__
u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
u32 gp_lvl = inl(gpio_base + GP_LVL);
u32 flags = 0;
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
if (gp_lvl3 & (1 << (GPIO_SPI_WP-64)))
flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
flags |= (1 << FLAG_REC_MODE);
/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
if (gp_lvl & (1 << GPIO_DEV_MODE))
flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
#endif
}
开发者ID:killbug2004，项目名称:coreboot，代码行数:22，代码来源:chromeos.c
示例2: ide_init
static void ide_init(struct device *dev)
{
struct southbridge_nvidia_ck804_config *conf;
u32 dword;
u16 word;
u8 byte;
conf = dev->chip_info;
word = pci_read_config16(dev, 0x50);
/* Ensure prefetch is disabled. */
word &= ~((1 << 15) | (1 << 13));
if (conf->ide1_enable) {
/* Enable secondary IDE interface. */
word |= (1 << 0);
printk(BIOS_DEBUG, "IDE1 \t");
}
if (conf->ide0_enable) {
/* Enable primary IDE interface. */
word |= (1 << 1);
printk(BIOS_DEBUG, "IDE0\n");
}
word |= (1 << 12);
word |= (1 << 14);
pci_write_config16(dev, 0x50, word);
byte = 0x20; /* Latency: 64 --> 32 */
pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
}
开发者ID:DarkDefender，项目名称:coreboot，代码行数:39，代码来源:ide.c
示例3: vga_init
static void vga_init(device_t dev)
{
u8 reg8;
mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);
//*
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x3e, 0x02);
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config32(dev, 0x10, 0xa0000008);
pci_write_config32(dev, 0x14, 0xdd000000);
pci_write_config8(dev, 0x3c, 0x0b);
//*/
printk(BIOS_DEBUG, "Initializing VGA...\n");
pci_dev_init(dev);
if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return;
printk(BIOS_DEBUG, "Enable VGA console\n");
vga_enable_console();
/* It's not clear if these need to be programmed before or after
* the VGA bios runs. Try both, clean up later */
/* Set memory rate to 200MHz */
outb(0x3d, CRTM_INDEX);
reg8 = inb(CRTM_DATA);
reg8 &= 0x0f;
reg8 |= (0x3 << 4);
outb(0x3d, CRTM_INDEX);
outb(reg8, CRTM_DATA);
/* Set framebuffer size to 32mb */
reg8 = (32 / 4);
outb(0x39, SR_INDEX);
outb(reg8, SR_DATA);
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:39，代码来源:vga.c
示例4: usb_ehci_set_subsystem
static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
unsigned device)
{
u8 access_cntl;
access_cntl = pci_read_config8(dev, 0x80);
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
/* Restore protection. */
pci_write_config8(dev, 0x80, access_cntl);
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:22，代码来源:usb_ehci.c
示例5: intel_pch_finalize_smm
void intel_pch_finalize_smm(void)
{
/* Set SPI opcode menu */
RCBA16(0x3894) = SPI_OPPREFIX;
RCBA16(0x3896) = SPI_OPTYPE;
RCBA32(0x3898) = SPI_OPMENU_LOWER;
RCBA32(0x389c) = SPI_OPMENU_UPPER;
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
#if CONFIG_SPI_FLASH_SMM
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));
/* BIOS Interface Lockdown */
RCBA32_OR(0x3410, (1 << 0));
/* Function Disable SUS Well Lockdown */
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */
pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
}
开发者ID:DarkDefender，项目名称:coreboot，代码行数:39，代码来源:finalize.c
示例6: chrome_init
static void
chrome_init(struct device *dev)
{
uint32_t fb_size, fb_address;
fb_size = k8m890_host_fb_size_get();
if (!fb_size) {
printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
" ramcontroller!\n");
return;
}
fb_address = pci_read_config32(dev, 0x10);
fb_address &= ~0x0F;
if (!fb_address) {
printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n");
return;
}
printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
fb_size, fb_address);
//k8m890_host_fb_direct_set(fb_address);
#if CONFIG_VGA
/* Now set up the VGA console */
vga_io_init(); /* Enable full IO access */
chrome_vga_init(dev);
vga_textmode_init();
printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n");
/* if we don't have console, at least print something... */
vga_line_write(0, "Chrome VGA Textmode initialized.");
#endif /* CONFIG_VGA */
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:38，代码来源:chrome.c
示例7: ide_init
static void ide_init(struct device *dev)
{
struct southbridge_amd_sb800_config *conf;
/* Enable ide devices so the linux ide driver will work */
u32 dword;
u8 byte;
conf = dev->chip_info;
/* RPR9.1 disable MSI */
/* TODO: For A14, it should set as 1. I doubt it. */
dword = pci_read_config32(dev, 0x70);
dword &= ~(1 << 16);
pci_write_config32(dev, 0x70, dword);
/* Ultra DMA mode */
/* enable UDMA */
byte = pci_read_config8(dev, 0x54);
byte |= 1 << 0;
pci_write_config8(dev, 0x54, byte);
/* Enable I/O Access&& Bus Master */
dword = pci_read_config16(dev, 0x4);
dword |= 1 << 2;
pci_write_config16(dev, 0x4, dword);
/* set ide as primary, if you want to boot from IDE, you'd better set it
* in mainboard/Config.lb */
if (conf->boot_switch_sata_ide == 1) {
byte = pci_read_config8(dev, 0xAD);
byte |= 1 << 4;
pci_write_config8(dev, 0xAD, byte);
}
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
#endif
}
开发者ID:XVilka，项目名称:coreboot，代码行数:38，代码来源:ide.c
示例8: enable_hpet
static void enable_hpet(struct device *dev)
{
const unsigned long hpet_address = 0xfed00000;
uint32_t dword;
uint32_t code = (0 & 0x3);
dword = pci_read_config32(dev, GEN_CNTL);
dword |= (1 << 17); /* enable hpet */
/* Bits [16:15] Memory Address Range
* 00 FED0_0000h - FED0_03FFh
* 01 FED0_1000h - FED0_13FFh
* 10 FED0_2000h - FED0_23FFh
* 11 FED0_3000h - FED0_33FFh
*/
dword &= ~(3 << 15); /* clear it */
dword |= (code<<15);
pci_write_config32(dev, GEN_CNTL, dword);
printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:23，代码来源:lpc.c
示例9: native_init
static void native_init(struct device *dev)
{
struct resource *lfb_res;
struct resource *pio_res;
u32 physbase;
struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
struct northbridge_intel_x4x_config *conf = dev->chip_info;
lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
if (gtt_res && gtt_res->base) {
printk(BIOS_SPEW,
"Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
intel_gma_init(conf, res2mmio(gtt_res, 0, 0),
physbase, pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE");
}
开发者ID:lynxis，项目名称:coreboot-signed，代码行数:23，代码来源:gma.c
示例10: acpi_fill_madt
unsigned long acpi_fill_madt(unsigned long current)
{
device_t dev;
u32 dword;
u32 gsi_base=0;
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write SB700 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
IO_APIC_ADDR, gsi_base);
/* IOAPIC on rs5690 */
gsi_base += 24; /* SB700 has 24 IOAPIC entries. */
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2+1,
dword, gsi_base);
}
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edge-triggered, Active high */
/* create all subtables for processors */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
/* 1: LINT1 connect to NMI */
return current;
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:37，代码来源:acpi_tables.c
示例11: sdram_set_registers
static void sdram_set_registers(const struct mem_controller *ctrl)
{
static const u32 register_values[] = {
PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG,
PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0,
};
int i;
for (i = 0; i < ARRAY_SIZE(register_values); i += 3) {
device_t dev;
u32 where;
u32 reg;
dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
where = register_values[i] & 0xff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
}
开发者ID:lynxis，项目名称:coreboot-signed，代码行数:24，代码来源:raminit_ep80579.c
示例12: usb_init
static void usb_init(struct device *dev)
{
printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
//-------------- enable USB1.1 (SiS7001) -------------------------
{
uint8_t temp8;
int i=0;
while(SiS_SiS7001_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
temp8 &= SiS_SiS7001_init[i][1];
temp8 |= SiS_SiS7001_init[i][2];
pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
i++;
};
}
//-----------------------------------------------------------
#if DEBUG_USB
{
int i;
printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
if((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
printk(BIOS_DEBUG, "\n");
}
#endif
printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:36，代码来源:usb.c
示例13: set_gpio40_gfx
/*
* set gpio40 gfx
*/
static void set_gpio40_gfx(void)
{
u8 byte;
// u16 word;
u32 dword;
struct device *sm_dev;
/* disable the GPIO40 as CLKREQ2# function */
byte = pm_ioread(0xd3);
byte &= ~(1 << 7);
pm_iowrite(0xd3, byte);
/* disable the GPIO40 as CLKREQ3# function */
byte = pm_ioread(0xd4);
byte &= ~(1 << 0);
pm_iowrite(0xd4, byte);
/* enable pull up for GPIO68 */
byte = pm2_ioread(0xf1);
byte &= ~(1 << 4);
pm2_iowrite(0xf1, byte);
/* access the smbus extended register */
sm_dev = pcidev_on_root(0x14, 0);
/* set the gfx to 1x16 lanes */
printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
/* when the gpio40 is configured as GPIO, this will enable the output */
pci_write_config32(sm_dev, 0xf8, 0x4);
dword = pci_read_config32(sm_dev, 0xfc);
dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */
dword &= ~(1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
}
开发者ID:canistation，项目名称:coreboot，代码行数:39，代码来源:mainboard.c
示例14: ide_init
static void ide_init(struct device *dev)
{
struct southbridge_amd_sb700_config *conf;
/* Enable ide devices so the linux ide driver will work */
u32 dword;
u8 byte;
conf = dev->chip_info;
/* RPR9.1 disable MSI */
/* TODO: For A14, it should set as 1. I doubt it. */
dword = pci_read_config32(dev, 0x70);
dword &= ~(1 << 16);
pci_write_config32(dev, 0x70, dword);
/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
byte = pci_read_config8(dev, 0x54);
byte |= 0xf;
pci_write_config8(dev, 0x54, byte);
/* Enable I/O Access&& Bus Master */
dword = pci_read_config16(dev, 0x4);
dword |= 1 << 2;
pci_write_config16(dev, 0x4, dword);
/* set ide as primary, if you want to boot from IDE, you'd better set it
* in $vendor/$mainboard/devicetree.cb */
if (conf->boot_switch_sata_ide == 1) {
struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte = pci_read_config8(sm_dev, 0xAD);
byte |= 1 << 4;
pci_write_config8(sm_dev, 0xAD, byte);
}
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:36，代码来源:ide.c
示例15: igd_compute_ggc
void igd_compute_ggc(sysinfo_t *const sysinfo)
{
const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4);
if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
sysinfo->ggc = 0x0002;
else {
u8 gfxsize;
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
2MB GTT + 2MB shadow GTT (0x0b00) else. */
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
/* 4 for 32MB, default if not set in cmos */
gfxsize = 4;
}
/* Handle invalid cmos settings */
if (gfxsize > 12)
gfxsize = 4;
sysinfo->ggc = 0x0300 | ((gfxsize + 1) << 4);
if (!(capid & (1 << (48 - 32))))
sysinfo->ggc |= 0x0800;
}
}
开发者ID:siro20，项目名称:coreboot，代码行数:24，代码来源:igd.c
示例16: mainboard_init
static void mainboard_init(device_t dev)
{
struct southbridge_intel_i82801gx_config *config;
device_t dev0, idedev;
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
/* If we're resuming from suspend, blink suspend LED */
dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
ec_write(0x0c, 0xc7);
idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
/* legacy I/O connected */
pmh7_ultrabay_power_enable(1);
ec_write(0x0c, 0x84);
} else if (idedev && idedev->chip_info &&
h8_ultrabay_device_present()) {
config = idedev->chip_info;
config->ide_enable_primary = 1;
pmh7_ultrabay_power_enable(1);
ec_write(0x0c, 0x84);
} else {
pmh7_ultrabay_power_enable(0);
ec_write(0x0c, 0x04);
}
/* set dock status led */
ec_write(0x0c, 0x08);
ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09);
}
开发者ID:B-Rich，项目名称:coreboot，代码行数:36，代码来源:mainboard.c
示例17: acpi_fill_madt
unsigned long acpi_fill_madt(unsigned long current)
{
device_t dev;
u32 dword;
u32 gsi_base = 0;
u32 apicid_sp5100;
u32 apicid_sr5650;
/*
* AGESA v5 Apply apic enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
* For systems with < 16 APICs, put the Local-APICs at 0..n and
* put the IO-APICs at (n + 1)..z
*/
if (CONFIG_MAX_CPUS >= 16)
apicid_sp5100 = 0x0;
else
apicid_sp5100 = CONFIG_MAX_CPUS + 1;
apicid_sr5650 = apicid_sp5100 + 1;
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write sp5100 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_sp5100,
IO_APIC_ADDR,
0
);
/* IOAPIC on rs5690 */
gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_sr5650,
dword,
gsi_base
);
}
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
0, //BUS
0, //SOURCE
2, //gsirq
0 //flags
);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edge-triggered, Active high */
/* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
}
开发者ID:0ida，项目名称:coreboot，代码行数:63，代码来源:acpi_tables.c
示例18: mptable_init
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int i, bus_isa;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev = 0;
struct resource *res;
for(i=0; i<3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
}
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//IDE
outb(0x02, 0xc00); outb(0x0e, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
//SATA
outb(0x07, 0xc00); outb(0x0f, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
//USB
outb(0x01, 0xc00); outb(0x0a, 0xc01);
for(i=0;i<3;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
}
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
device_t dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts
pci_write_config32(dev, 0x6c, dword);
}
}
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
// AIC 8130 Galileo Technology...
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
}
//pci slot (on bcm5785)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
}
//onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
}
//onboard Broadcom
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
}
// First PCI-E x8
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
}
// Second PCI-E x8
//.........这里部分代码省略.........
开发者ID:cristim，项目名称:coreboot，代码行数:101，代码来源:mptable.c
示例19: sch_port_access_read
int sch_port_access_read(int port, int reg, int bytes)
{
pci_write_config32(PCI_DEV(0, 0, 0), MCR,
(MSG_OPCODE_READ | (port << 16) | (reg << 8)));
return pci_read_config32(PCI_DEV(0, 0, 0), MDR);
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:6，代码来源:port_access.c
示例20: lpc_enable_childrens_resources
/**
* @brief Enable resources for children devices
*
* @param dev the device whose children's resources are to be enabled
*
*/
void lpc_enable_childrens_resources(device_t dev)
{
struct bus *link;
u32 reg, reg_x;
int var_num = 0;
u16 reg_var[3];
printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
reg = pci_read_config32(dev, 0x44);
reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) {
device_t child;
for (child = link->children; child;
child = child->sibling) {
if (child->enabled
&& (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
for (res = child->resource_list; res; res = res->next) {
u32 base, end; /* don't need long long */
if (!(res->flags & IORESOURCE_IO))
continue;
base = res->base;
end = resource_end(res);
/*
printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
dev_path(child), base, end);
*/
switch (base) {
case 0x60: /* KB */
case 0x64: /* MS */
reg |= (1 << 29);
break;
case 0x3f8: /* COM1 */
reg |= (1 << 6);
break;
case 0x2f8: /* COM2 */
reg |= (1 << 7);
break;
case 0x378: /* Parallel 1 */
reg |= (1 << 0);
break;
case 0x3f0: /* FD0 */
reg |= (1 << 26);
break;
case 0x220: /* Audio 0 */
reg |= (1 << 8);
break;
case 0x300: /* Midi 0 */
reg |= (1 << 18);
break;
case 0x400:
reg_x |= (1 << 16);
break;
case 0x480:
reg_x |= (1 << 17);
break;
case 0x500:
reg_x |= (1 << 18);
break;
case 0x580:
reg_x |= (1 << 19);
break;
case 0x4700:
reg_x |= (1 << 22);
break;
case 0xfd60:
reg_x |= (1 << 23);
break;
default:
if (var_num >= 3)
continue; /* only 3 var ; compact them ? */
switch (var_num) {
case 0:
reg_x |= (1 << 2);
break;
case 1:
reg_x |= (1 << 24);
break;
case 2:
reg_x |= (1 << 25);
break;
}
reg_var[var_num++] =
base & 0xffff;
}
}
}
}
}
pci_write_config32(dev, 0x44, reg);
pci_write_config32(dev, 0x48, reg_x);
/* Set WideIO for as many IOs found (fall through is on purpose) */
switch (var_num) {
//.........这里部分代码省略.........
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:101，代码来源:lpc.c
注：本文中的pci_read_config32函数示例由纯净天空整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。 |
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