static int
fm801_pci_probe( device_t dev )
{
	int id;

	if ((id = pci_get_devid(dev)) == PCI_DEVICE_FORTEMEDIA1 ) {
		device_set_desc(dev, "Forte Media FM801 Audio Controller");
		return BUS_PROBE_DEFAULT;
	}
/*
	if ((id = pci_get_devid(dev)) == PCI_DEVICE_FORTEMEDIA2 ) {
		device_set_desc(dev, "Forte Media FM801 Joystick (Not Supported)");
		return ENXIO;
	}
*/
	return ENXIO;
}

static int
intsmb_probe(device_t dev)
{
	const struct intsmb_device *isd;
	uint32_t devid;
	size_t i;

	devid = pci_get_devid(dev);
	for (i = 0; i < nitems(intsmb_products); i++) {
		isd = &intsmb_products[i];
		if (isd->devid == devid) {
			device_set_desc(dev, isd->description);
			return (BUS_PROBE_DEFAULT);
		}
	}
	return (ENXIO);
}

static int
isci_probe (device_t device)
{
    u_int32_t	type = pci_get_devid(device);
    struct _pcsid	*ep = pci_ids;

    while (ep->type && ep->type != type)
        ++ep;

    if (ep->desc)
    {
        device_set_desc(device, ep->desc);
        return (BUS_PROBE_DEFAULT);
    }
    else
        return (ENXIO);
}

static int
xrpu_probe(device_t self)
{
	char *desc;

	desc = NULL;
	switch (pci_get_devid(self)) {
	case 0x6216133e:
		desc = "VCC Hotworks-I xc6216";
		break;
	}
	if (desc == NULL)
		return ENXIO;

	device_set_desc(self, desc);
	return 0;
}

static int
ntb_attach(device_t device)
{
	struct ntb_softc *ntb;
	struct ntb_hw_info *p;
	int error;

	ntb = DEVICE2SOFTC(device);
	p = ntb_get_device_info(pci_get_devid(device));

	ntb->device = device;
	ntb->type = p->type;
	ntb->features = p->features;

	/* Heartbeat timer for NTB_SOC since there is no link interrupt */
	callout_init(&ntb->heartbeat_timer, 1);
	callout_init(&ntb->lr_timer, 1);

	if (ntb->type == NTB_SOC)
		error = ntb_detect_soc(ntb);
	else
		error = ntb_detect_xeon(ntb);
	if (error)
		goto out;

	error = ntb_map_pci_bars(ntb);
	if (error)
		goto out;
	if (ntb->type == NTB_SOC)
		error = ntb_setup_soc(ntb);
	else
		error = ntb_setup_xeon(ntb);
	if (error)
		goto out;
	error = ntb_setup_interrupts(ntb);
	if (error)
		goto out;

	pci_enable_busmaster(ntb->device);

out:
	if (error != 0)
		ntb_detach(device);
	return (error);
}

static int
piix_probe (device_t dev)
{
	u_int32_t	d;

	switch (pci_get_devid(dev)) {
	case 0x71138086:
		d = pci_read_config(dev, 0x4, 2);
		if (!(d & 1))
			return 0;	/* IO space not mapped */
		d = pci_read_config(dev, 0x40, 4);
		piix_timecounter_address = (d & 0xffc0) + 8;
		piix_timecounter.tc_frequency = piix_freq;
		init_timecounter(&piix_timecounter);
		return (ENXIO);
	};
	return (ENXIO);
}

static int
fwohci_pci_init(device_t self)
{
	int olatency, latency, ocache_line, cache_line;
	uint16_t cmd;

	cmd = pci_read_config(self, PCIR_COMMAND, 2);
	cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
#if 1  /* for broken hardware */
	cmd &= ~PCIM_CMD_MWRICEN; 
#endif
	pci_write_config(self, PCIR_COMMAND, cmd, 2);

	/*
	 * Some Sun PCIO-2 FireWire controllers have their intpin register
	 * bogusly set to 0, although it should be 3. Correct that.
	 */
	if (pci_get_devid(self) == (FW_VENDORID_SUN | FW_DEVICE_PCIO2FW) &&
	    pci_get_intpin(self) == 0)
		pci_set_intpin(self, 3);

	latency = olatency = pci_read_config(self, PCIR_LATTIMER, 1);
#define DEF_LATENCY 0x20
	if (olatency < DEF_LATENCY) {
		latency = DEF_LATENCY;
		pci_write_config(self, PCIR_LATTIMER, latency, 1);
	}

	cache_line = ocache_line = pci_read_config(self, PCIR_CACHELNSZ, 1);
#define DEF_CACHE_LINE 8
	if (ocache_line < DEF_CACHE_LINE) {
		cache_line = DEF_CACHE_LINE;
		pci_write_config(self, PCIR_CACHELNSZ, cache_line, 1);
	}

	if (firewire_debug) {
		device_printf(self, "latency timer %d -> %d.\n",
			olatency, latency);
		device_printf(self, "cache size %d -> %d.\n",
			ocache_line, cache_line);
	}

	return 0;
}

static int
intsmb_probe(device_t dev)
{

	switch (pci_get_devid(dev)) {
	case 0x71138086:	/* Intel 82371AB */
	case 0x719b8086:	/* Intel 82443MX */
#if 0
	/* Not a good idea yet, this stops isab0 functioning */
	case 0x02001166:	/* ServerWorks OSB4 */
#endif
		device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
		break;
	default:
		return (ENXIO);
	}

	return (BUS_PROBE_DEFAULT);
}

static const char *
ohci_pci_match(device_t self)
{
	u_int32_t device_id = pci_get_devid(self);

	switch (device_id) {
	case PCI_OHCI_DEVICEID_ALADDIN_V:
		return (ohci_device_aladdin_v);
	case PCI_OHCI_DEVICEID_AMD756:
		return (ohci_device_amd756);
	case PCI_OHCI_DEVICEID_AMD766:
		return (ohci_device_amd766);
	case PCI_OHCI_DEVICEID_CS5536:
		return (ohci_device_cs5536);
	case PCI_OHCI_DEVICEID_SB400_1:
	case PCI_OHCI_DEVICEID_SB400_2:
		return (ohci_device_sb400);
	case PCI_OHCI_DEVICEID_USB0670:
		return (ohci_device_usb0670);
	case PCI_OHCI_DEVICEID_USB0673:
		return (ohci_device_usb0673);
	case PCI_OHCI_DEVICEID_FIRELINK:
		return (ohci_device_firelink);
	case PCI_OHCI_DEVICEID_NEC:
		return (ohci_device_nec);
	case PCI_OHCI_DEVICEID_NFORCE3:
		return (ohci_device_nforce3);
	case PCI_OHCI_DEVICEID_SIS5571:
		return (ohci_device_sis5571);
	case PCI_OHCI_DEVICEID_KEYLARGO:
		return (ohci_device_keylargo);
	case PCI_OHCI_DEVICEID_PCIO2USB:
		return (ohci_device_pcio2usb);
	default:
		if (pci_get_class(self) == PCIC_SERIALBUS
		    && pci_get_subclass(self) == PCIS_SERIALBUS_USB
		    && pci_get_progif(self) == PCI_INTERFACE_OHCI) {
			return (ohci_device_generic);
		}
	}

	return NULL;		/* dunno */
}

static void
ofw_pcib_setup_device(device_t bus, device_t child)
{
	int i;
	uint16_t reg;

	switch (pci_get_vendor(bus)) {
	/*
	 * For PLX PEX 8532 issue 64 TLPs to the child from the downstream
	 * port to the child device in order to work around a hardware bug.
	 */
	case PCI_VENDOR_PLX:
		for (i = 0, reg = 0; i < 64; i++)
			reg |= pci_get_devid(child);
		break;
	}

	OFW_PCI_SETUP_DEVICE(device_get_parent(bus), child);
}

/*
 * Cypress chipset support functions
 */
static int
ata_cypress_probe(device_t dev)
{
    struct ata_pci_controller *ctlr = device_get_softc(dev);

    /*
     * the Cypress chip is a mess, it contains two ATA functions, but
     * both channels are visible on the first one.
     * simply ignore the second function for now, as the right
     * solution (ignoring the second channel on the first function)
     * doesn't work with the crappy ATA interrupt setup on the alpha.
     */
    if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
	pci_get_function(dev) == 1 &&
	pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
	device_set_desc(dev, "Cypress 82C693 ATA controller");
	ctlr->chipinit = ata_cypress_chipinit;
	return (BUS_PROBE_LOW_PRIORITY);
    }
    return ENXIO;
}

static int
ed_pci_attach(device_t dev)
{
	struct	ed_softc *sc = device_get_softc(dev);
	int	error = ENXIO;

	/*
	 * Probe RTL8029 cards, but allow failure and try as a generic
	 * ne-2000.  QEMU 0.9 and earlier use the RTL8029 PCI ID, but
	 * are areally just generic ne-2000 cards.
	 */
	if (pci_get_devid(dev) == ED_RTL8029_PCI_ID)
		error = ed_probe_RTL80x9(dev, PCIR_BAR(0), 0);
	if (error)
		error = ed_probe_Novell(dev, PCIR_BAR(0),
		    ED_FLAGS_FORCE_16BIT_MODE);
	if (error) {
		ed_release_resources(dev);
		return (error);
	}
	ed_Novell_read_mac(sc);

	error = ed_alloc_irq(dev, 0, RF_SHAREABLE);
	if (error) {
		ed_release_resources(dev);
		return (error);
	}
	if (sc->sc_media_ioctl == NULL)
		ed_gen_ifmedia_init(sc);
	error = ed_attach(dev);
	if (error) {
		ed_release_resources(dev);
		return (error);
	}
	error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
	    NULL, edintr, sc, &sc->irq_handle);
	if (error)
		ed_release_resources(dev);
	return (error);
}

static int
piix_probe(device_t dev)
{
	u_int32_t d;

	if (devclass_get_device(devclass_find("acpi"), 0) != NULL)
		return (ENXIO);
	switch (pci_get_devid(dev)) {
	case 0x71138086:
		device_set_desc(dev, "PIIX Timecounter");
		break;
	default:
		return (ENXIO);
	}

	d = pci_read_config(dev, PCIR_COMMAND, 2);
	if (!(d & PCIM_CMD_PORTEN)) {
		device_printf(dev, "PIIX I/O space not mapped\n");
		return (ENXIO);
	}
	return (0);
}

static int
ismt_probe(device_t dev)
{
	const char *desc;

	switch (pci_get_devid(dev)) {
	case ID_INTEL_S1200_SMT0:
		desc = "Atom Processor S1200 SMBus 2.0 Controller 0";
		break;
	case ID_INTEL_S1200_SMT1:
		desc = "Atom Processor S1200 SMBus 2.0 Controller 1";
		break;
	case ID_INTEL_C2000_SMT:
		desc = "Atom Processor C2000 SMBus 2.0";
		break;
	default:
		return (ENXIO);
	}

	device_set_desc(dev, desc);
	return (BUS_PROBE_DEFAULT);
}

static boolean_t
ioat_model_resets_msix(struct ioat_softc *ioat)
{
	u_int32_t pciid;

	pciid = pci_get_devid(ioat->device);
	switch (pciid) {
		/* BWD: */
	case 0x0c508086:
	case 0x0c518086:
	case 0x0c528086:
	case 0x0c538086:
		/* BDXDE: */
	case 0x6f508086:
	case 0x6f518086:
	case 0x6f528086:
	case 0x6f538086:
		return (TRUE);
	}

	return (FALSE);
}

static int
ntb_attach(device_t device)
{
	struct ntb_softc *ntb = DEVICE2SOFTC(device);
	struct ntb_hw_info *p = ntb_get_device_info(pci_get_devid(device));
	int error;

	ntb->device = device;
	ntb->type = p->type;
	ntb->features = p->features;

	/* Heartbeat timer for NTB_SOC since there is no link interrupt */
	callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE);
	callout_init(&ntb->lr_timer, CALLOUT_MPSAFE);

	DETACH_ON_ERROR(ntb_map_pci_bars(ntb));
	DETACH_ON_ERROR(ntb_initialize_hw(ntb));
	DETACH_ON_ERROR(ntb_setup_interrupts(ntb));

	pci_enable_busmaster(ntb->device);

	return (error);
}

static int
ichsmb_pci_probe(device_t dev)
{
	/* Check PCI identifier */
	switch (pci_get_devid(dev)) {
	case ID_82801AA:
		device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller");
		break;
	case ID_82801AB:
		device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller");
		break;
	case ID_82801BA:
		device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller");
		break;
	case ID_82801CA:
		device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller");
		break;
	case ID_82801DC:
		device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller");
		break;
	case ID_82801EB:
		device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller");
		break;
	default:
		if (pci_get_class(dev) == PCIC_SERIALBUS
		    && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS
		    && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) {
			device_set_desc(dev, "SMBus controller");
			return (-2);		/* XXX */
		}
		return (ENXIO);
	}

	/* Done */
	return (ichsmb_probe(dev));
}

const struct ata_chip_id *
ata_find_chip(device_t dev, const struct ata_chip_id *index, int slot)
{
    device_t *children;
    int nchildren, i;

    if (device_get_children(device_get_parent(dev), &children, &nchildren))
	return NULL;

    while (index->chipid != 0) {
	for (i = 0; i < nchildren; i++) {
	    if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
		 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
		pci_get_devid(children[i]) == index->chipid &&
		pci_get_revid(children[i]) >= index->chiprev) {
		kfree(children, M_TEMP);
		return index;
	    }
	}
	index++;
    }
    kfree(children, M_TEMP);
    return NULL;
}

static int
ofw_pcib_attach(device_t dev)
{
	struct ofw_pcib_gen_softc *sc;

	sc = device_get_softc(dev);

	switch (pci_get_devid(dev)) {
	/*
	 * The ALi M5249 found in Fire-based machines by definition must me
	 * subtractive as they have a ISA bridge on their secondary side but
	 * don't indicate this in the class code although the ISA I/O range
	 * isn't included in their bridge decode.
	 */
	case PCI_DEVID_ALI_M5249:
		sc->ops_pcib_sc.flags |= PCIB_SUBTRACTIVE;
		break;
	}

	switch (pci_get_vendor(dev)) {
	/*
	 * Concurrently write the primary and secondary bus numbers in order
	 * to work around a bug in PLX PEX 8114 causing the internal shadow
	 * copies of these not to be updated when setting them bytewise.
	 */
	case PCI_VENDOR_PLX:
		pci_write_config(dev, PCIR_PRIBUS_1,
		    pci_read_config(dev, PCIR_SECBUS_1, 1) << 8 |
		    pci_read_config(dev, PCIR_PRIBUS_1, 1), 2);
		break;
	}

	ofw_pcib_gen_setup(dev);
	pcib_attach_common(dev);
	return (pcib_attach_child(dev));
}

//.........这里部分代码省略.........
		sprintf(sc->sc_vendor, "Apple");
		break;
	case PCI_EHCI_VENDORID_ATI:
		sprintf(sc->sc_vendor, "ATI");
		break;
	case PCI_EHCI_VENDORID_CMDTECH:
		sprintf(sc->sc_vendor, "CMDTECH");
		break;
	case PCI_EHCI_VENDORID_INTEL:
		sprintf(sc->sc_vendor, "Intel");
		break;
	case PCI_EHCI_VENDORID_NEC:
		sprintf(sc->sc_vendor, "NEC");
		break;
	case PCI_EHCI_VENDORID_OPTI:
		sprintf(sc->sc_vendor, "OPTi");
		break;
	case PCI_EHCI_VENDORID_PHILIPS:
		sprintf(sc->sc_vendor, "Philips");
		break;
	case PCI_EHCI_VENDORID_SIS:
		sprintf(sc->sc_vendor, "SiS");
		break;
	case PCI_EHCI_VENDORID_NVIDIA:
	case PCI_EHCI_VENDORID_NVIDIA2:
		sprintf(sc->sc_vendor, "nVidia");
		break;
	case PCI_EHCI_VENDORID_VIA:
		sprintf(sc->sc_vendor, "VIA");
		break;
	default:
		if (bootverbose)
			device_printf(self, "(New EHCI DeviceId=0x%08x)\n",
			    pci_get_devid(self));
		sprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
	}

#if (__FreeBSD_version >= 700031)
	err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
	    NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
#else
	err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
	    (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
#endif
	if (err) {
		device_printf(self, "Could not setup irq, %d\n", err);
		sc->sc_intr_hdl = NULL;
		goto error;
	}
	ehci_pci_take_controller(self);

	/* Undocumented quirks taken from Linux */

	switch (pci_get_vendor(self)) {
	case PCI_EHCI_VENDORID_ATI:
		/* SB600 and SB700 EHCI quirk */
		switch (pci_get_device(self)) {
		case 0x4386:
			ehci_pci_ati_quirk(self, 0);
			break;
		case 0x4396:
			ehci_pci_ati_quirk(self, 1);
			break;
		default:
			break;
		}