static int __init rd88f6183ap_ge_pci_init(void)
{
	if (machine_is_rd88f6183ap_ge()) {
		orion5x_pci_disable();
		pci_common_init(&rd88f6183ap_ge_pci);
	}

	return 0;
}

static int __init iq31244_pci_init(void)
{
	if (is_ep80219())
		pci_common_init(&ep80219_pci);
	else if (machine_is_iq31244()) {
		if (is_80219()) {
			printk("note: iq31244 board type has been selected\n");
			printk("note: to select ep80219 operation:\n");
			printk("\t1/ specify \"force_ep80219\" on the kernel"
				" command line\n");
			printk("\t2/ update boot loader to pass"
				" the ep80219 id: %d\n", MACH_TYPE_EP80219);
		}
		pci_common_init(&iq31244_pci);
	}

	return 0;
}

static int __init rd88f5181l_fxo_pci_init(void)
{
	if (machine_is_rd88f5181l_fxo()) {
		orion5x_pci_set_cardbus_mode();
		pci_common_init(&rd88f5181l_fxo_pci);
	}

	return 0;
}

static int __init kurobox_pro_pci_init(void)
{
	if (machine_is_kurobox_pro()) {
		orion5x_pci_disable();
		pci_common_init(&kurobox_pro_pci);
	}

	return 0;
}

static int __init dns323_pci_init(void)
{
	/* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
	 * gets in the way of initialising the SATA controller.
	 */
	if (machine_is_dns323() && system_rev == DNS323_REV_A1)
		pci_common_init(&dns323_pci);

	return 0;
}

static int __devinit mcs8140_pci_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret, irq;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "failed to get mem resource 0\n");
		return -ENODEV;
	}

	mcs8140_pci_master_base = devm_ioremap(&pdev->dev, res->start,
					resource_size(res));
	if (!mcs8140_pci_master_base) {
		dev_err(&pdev->dev, "failed to remap PCI master regs\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "failed to get mem resource 1\n");
		return -ENOMEM;
	}

	mcs8140_eeprom_emu_base = devm_ioremap(&pdev->dev, res->start,
					resource_size(res));
	if (!mcs8140_eeprom_emu_base) {
		dev_err(&pdev->dev, "failed to remap EEPROM regs\n");
		return -ENOMEM;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "failed to get pci abort irq\n");
		return -ENODEV;
	}

	/* Setup static mappins for PCI CFG space */
	iotable_init(mcs8140_pci_io_desc, ARRAY_SIZE(mcs8140_pci_io_desc));

	pcibios_min_io = MCS8140_PCI_HOST_BASE;
	pcibios_min_mem = MCS8140_PCI_HOST_BASE + MCS8140_PCI_PRE_BASE;

	mcs8140_data_abort_init();
	ret = mcs8140_pci_abort_irq_init(irq);
	if (ret) {
		dev_err(&pdev->dev, "failed to setup abort irq\n");
		return ret;
	}

	pci_common_init(&mcs8140_pci);

	return 0;
}

void __init kirkwood_pcie_init(unsigned int portmask)
{
	if (portmask & KW_PCIE0)
		add_pcie_port(0, PCIE_VIRT_BASE);

	if (portmask & KW_PCIE1)
		add_pcie_port(1, PCIE1_VIRT_BASE);

	kirkwood_pci.nr_controllers = num_pcie_ports;
	pci_common_init(&kirkwood_pci);
}

void __init dove_pcie_init(int init_port0, int init_port1)
{
	vga_base = DOVE_PCIE0_MEM_PHYS_BASE;

	if (init_port0)
		add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);

	if (init_port1)
		add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);

	pci_common_init(&dove_pci);
}

static int __init shark_pci_init(void)
{
	if (!machine_is_shark())
		return;

	pcibios_min_io = 0x6000;
	pcibios_min_mem = 0x50000000;
	vga_base = 0xe8000000;

	pci_common_init(&shark_pci);

	return 0;
}

int __init ixdp2800_pci_init(void)
{
	if (machine_is_ixdp2800()) {
		struct pci_dev *dev;

		pci_common_init(&ixdp2800_pci);
		if (ixdp2x00_master_npu()) {
			dev = pci_find_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
			pci_remove_bus_device(dev);

			ixdp2800_master_enable_slave();
			ixdp2800_master_wait_for_slave_bus_scan();
		} else {
			dev = pci_find_slot(1, IXDP2800_MASTER_ENET_DEVFN);
			pci_remove_bus_device(dev);
		}
	}

	return 0;
}

void __init mv78xx0_pcie_init(int init_port0, int init_port1)
{
	vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;

	if (init_port0) {
		add_pcie_port(0, 0, PCIE00_VIRT_BASE);
		if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
			add_pcie_port(0, 1, PCIE01_VIRT_BASE);
			add_pcie_port(0, 2, PCIE02_VIRT_BASE);
			add_pcie_port(0, 3, PCIE03_VIRT_BASE);
		}
	}

	if (init_port1) {
		add_pcie_port(1, 0, PCIE10_VIRT_BASE);
		if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
			add_pcie_port(1, 1, PCIE11_VIRT_BASE);
			add_pcie_port(1, 2, PCIE12_VIRT_BASE);
			add_pcie_port(1, 3, PCIE13_VIRT_BASE);
		}
	}

	pci_common_init(&mv78xx0_pci);
}

static int __init shark_pci_init(void)
{
	if (machine_is_shark())
		pci_common_init(&shark_pci);
	return 0;
}

int __init avila_pci_init(void)
{
	if (machine_is_avila() || machine_is_loft())
		pci_common_init(&avila_pci);
	return 0;
}

int __init gateway7001_pci_init(void)
{
	if (machine_is_gateway7001())
		pci_common_init(&gateway7001_pci);
	return 0;
}

int __init pronghornmetro_pci_init(void)
{
	if (machine_is_pronghorn_metro())
		pci_common_init(&pronghornmetro_pci);
	return 0;
}

void __init kirkwood_pcie_init(void)
{
	pci_common_init(&kirkwood_pci);
}

int __init enp2611_pci_init(void)
{
	pci_common_init(&enp2611_pci);
	return 0;
}

int __init sg8100_pci_init(void)
{
	if (machine_is_sg8100())
		pci_common_init(&sg8100_pci);
	return 0;
}

int __init coyote_pci_init(void)
{
	if (machine_is_adi_coyote())
		pci_common_init(&coyote_pci);
	return 0;
}

static int __init ftv_pci_init(void)
{
	if (machine_is_ftvpci())
		pci_common_init(&ftv_pci);
	return 0;
}