static void intc_disable_or_mask(struct irq_data *d)
{
	pr_debug("disable: %d\n", d->irq);
	out_be32(INTC_BASE + CIE, 1 << d->irq);
}

/*
 * create the endpoint structure
 *
 * arguments:
 * usb		A pointer to the data structure of the USB
 * data_mem	The data memory partition(BUS)
 * ring_len	TD ring length
 */
u32 fhci_create_ep(struct fhci_usb *usb, enum fhci_mem_alloc data_mem,
			   u32 ring_len)
{
	struct endpoint *ep;
	struct usb_td __iomem *td;
	unsigned long ep_offset;
	char *err_for = "enpoint PRAM";
	int ep_mem_size;
	u32 i;

	/* we need at least 3 TDs in the ring */
	if (!(ring_len > 2)) {
		fhci_err(usb->fhci, "illegal TD ring length parameters\n");
		return -EINVAL;
	}

	ep = kzalloc(sizeof(*ep), GFP_KERNEL);
	if (!ep)
		return -ENOMEM;

	ep_mem_size = ring_len * sizeof(*td) + sizeof(struct fhci_ep_pram);
	ep_offset = cpm_muram_alloc(ep_mem_size, 32);
	if (IS_ERR_VALUE(ep_offset))
		goto err;
	ep->td_base = cpm_muram_addr(ep_offset);

	/* zero all queue pointers */
	if (cq_new(&ep->conf_frame_Q, ring_len + 2) ||
	    cq_new(&ep->empty_frame_Q, ring_len + 2) ||
	    cq_new(&ep->dummy_packets_Q, ring_len + 2)) {
		err_for = "frame_queues";
		goto err;
	}

	for (i = 0; i < (ring_len + 1); i++) {
		struct packet *pkt;
		u8 *buff;

		pkt = kmalloc(sizeof(*pkt), GFP_KERNEL);
		if (!pkt) {
			err_for = "frame";
			goto err;
		}

		buff = kmalloc(1028 * sizeof(*buff), GFP_KERNEL);
		if (!buff) {
			kfree(pkt);
			err_for = "buffer";
			goto err;
		}
		cq_put(&ep->empty_frame_Q, pkt);
		cq_put(&ep->dummy_packets_Q, buff);
	}

	/* we put the endpoint parameter RAM right behind the TD ring */
	ep->ep_pram_ptr = (void __iomem *)ep->td_base + sizeof(*td) * ring_len;

	ep->conf_td = ep->td_base;
	ep->empty_td = ep->td_base;

	ep->already_pushed_dummy_bd = false;

	/* initialize tds */
	td = ep->td_base;
	for (i = 0; i < ring_len; i++) {
		out_be32(&td->buf_ptr, 0);
		out_be16(&td->status, 0);
		out_be16(&td->length, 0);
		out_be16(&td->extra, 0);
		td++;
	}
	td--;
	out_be16(&td->status, TD_W); /* for last TD set Wrap bit */
	out_be16(&td->length, 0);

	/* endpoint structure has been created */
	usb->ep0 = ep;

	return 0;
err:
	fhci_ep0_free(usb);
	kfree(ep);
	fhci_err(usb->fhci, "no memory for the %s\n", err_for);
	return -ENOMEM;
}

/*
 * Submitting a data frame to a specified endpoint of a USB device
 * The frame is put in the driver's transmit queue for this endpoint
 *
 * Arguments:
 * usb          A pointer to the USB structure
 * pkt          A pointer to the user frame structure
 * trans_type   Transaction tyep - IN,OUT or SETUP
 * dest_addr    Device address - 0~127
 * dest_ep      Endpoint number of the device - 0~16
 * trans_mode   Pipe type - ISO,Interrupt,bulk or control
 * dest_speed   USB speed - Low speed or FULL speed
 * data_toggle  Data sequence toggle - 0 or 1
 */
u32 fhci_host_transaction(struct fhci_usb *usb,
			  struct packet *pkt,
			  enum fhci_ta_type trans_type,
			  u8 dest_addr,
			  u8 dest_ep,
			  enum fhci_tf_mode trans_mode,
			  enum fhci_speed dest_speed, u8 data_toggle)
{
	struct endpoint *ep = usb->ep0;
	struct usb_td __iomem *td;
	u16 extra_data;
	u16 td_status;

	fhci_usb_disable_interrupt(usb);
	/* start from the next BD that should be filled */
	td = ep->empty_td;
	td_status = in_be16(&td->status);

	if (td_status & TD_R && in_be16(&td->length)) {
		/* if the TD is not free */
		fhci_usb_enable_interrupt(usb);
		return -1;
	}

	/* get the next TD in the ring */
	ep->empty_td = next_bd(ep->td_base, ep->empty_td, td_status);
	fhci_usb_enable_interrupt(usb);
	pkt->priv_data = td;
	out_be32(&td->buf_ptr, virt_to_phys(pkt->data));
	/* sets up transaction parameters - addr,endp,dir,and type */
	extra_data = (dest_ep << TD_ENDP_SHIFT) | dest_addr;
	switch (trans_type) {
	case FHCI_TA_IN:
		extra_data |= TD_TOK_IN;
		break;
	case FHCI_TA_OUT:
		extra_data |= TD_TOK_OUT;
		break;
	case FHCI_TA_SETUP:
		extra_data |= TD_TOK_SETUP;
		break;
	}
	if (trans_mode == FHCI_TF_ISO)
		extra_data |= TD_ISO;
	out_be16(&td->extra, extra_data);

	/* sets up the buffer descriptor */
	td_status = ((td_status & TD_W) | TD_R | TD_L | TD_I | TD_CNF);
	if (!(pkt->info & PKT_NO_CRC))
		td_status |= TD_TC;

	switch (trans_type) {
	case FHCI_TA_IN:
		if (data_toggle)
			pkt->info |= PKT_PID_DATA1;
		else
			pkt->info |= PKT_PID_DATA0;
		break;
	default:
		if (data_toggle) {
			td_status |= TD_PID_DATA1;
			pkt->info |= PKT_PID_DATA1;
		} else {
			td_status |= TD_PID_DATA0;
			pkt->info |= PKT_PID_DATA0;
		}
		break;
	}

	if ((dest_speed == FHCI_LOW_SPEED) &&
	    (usb->port_status == FHCI_PORT_FULL))
		td_status |= TD_LSP;

	out_be16(&td->status, td_status);

	/* set up buffer length */
	if (trans_type == FHCI_TA_IN)
		out_be16(&td->length, pkt->len + CRC_SIZE);
	else
		out_be16(&td->length, pkt->len);

	/* put the frame to the confirmation queue */
	cq_put(&ep->conf_frame_Q, pkt);

	if (cq_howmany(&ep->conf_frame_Q) == 1)
		out_8(&usb->fhci->regs->usb_comm, USB_CMD_STR_FIFO);
//.........这里部分代码省略.........

static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
	fsl_lbc_t *regs = LBC_BASE_ADDR;
	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
	const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
	const int block_shift = large ? 17 : 14;
	const int block_size = 1 << block_shift;
	const int page_size = large ? 2048 : 512;
	const int bad_marker = large ? page_size + 0 : page_size + 5;
	int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
	int pos = 0;

	if (offs & (block_size - 1)) {
		puts("bad offset\n");
		for (;;);
	}

	if (large) {
		fmr |= FMR_ECCM;
		out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
		                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
		out_be32(&regs->fir,
		         (FIR_OP_CW0 << FIR_OP0_SHIFT) |
		         (FIR_OP_CA  << FIR_OP1_SHIFT) |
		         (FIR_OP_PA  << FIR_OP2_SHIFT) |
		         (FIR_OP_CW1 << FIR_OP3_SHIFT) |
		         (FIR_OP_RBW << FIR_OP4_SHIFT));
	} else {
		out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
		out_be32(&regs->fir,
		         (FIR_OP_CW0 << FIR_OP0_SHIFT) |
		         (FIR_OP_CA  << FIR_OP1_SHIFT) |
		         (FIR_OP_PA  << FIR_OP2_SHIFT) |
		         (FIR_OP_RBW << FIR_OP3_SHIFT));
	}

	out_be32(&regs->fbcr, 0);
	clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);

	while (pos < uboot_size) {
		int i = 0;
		out_be32(&regs->fbar, offs >> block_shift);

		do {
			int j;
			unsigned int page_offs = (offs & (block_size - 1)) << 1;

			out_be32(&regs->ltesr, ~0);
			out_be32(&regs->lteatr, 0);
			out_be32(&regs->fpar, page_offs);
			out_be32(&regs->fmr, fmr);
			out_be32(&regs->lsor, 0);
			nand_wait();

			page_offs %= WINDOW_SIZE;

			/*
			 * If either of the first two pages are marked bad,
			 * continue to the next block.
			 */
			if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
				puts("skipping\n");
				offs = (offs + block_size) & ~(block_size - 1);
				pos &= ~(block_size - 1);
				break;
			}

			for (j = 0; j < page_size; j++)
				dst[pos + j] = buf[page_offs + j];

			pos += page_size;
			offs += page_size;
		} while ((offs & (block_size - 1)) && (pos < uboot_size));
	}
}

/* FIXME: If any other users of GPIO crop up, then these will have to
 * have some sort of global synchronization to avoid races with other
 * pins on the same port.  The ideal solution would probably be to
 * bind the ports to a GPIO driver, and have this be a client of it.
 */
static inline void bb_set(u32 __iomem *p, u32 m)
{
    out_be32(p, in_be32(p) | m);
}

unsigned int cpm_pic_init(void)
{
	struct device_node *np = NULL;
	struct resource res;
	unsigned int sirq = NO_IRQ, hwirq, eirq;
	int ret;

	pr_debug("cpm_pic_init\n");

	np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
	if (np == NULL)
		np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
	if (np == NULL) {
		printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
		return sirq;
	}

	ret = of_address_to_resource(np, 0, &res);
	if (ret)
		goto end;

	cpic_reg = ioremap(res.start, resource_size(&res));
	if (cpic_reg == NULL)
		goto end;

	sirq = irq_of_parse_and_map(np, 0);
	if (sirq == NO_IRQ)
		goto end;

	/* Initialize the CPM interrupt controller. */
	hwirq = (unsigned int)virq_to_hw(sirq);
	out_be32(&cpic_reg->cpic_cicr,
	    (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
		((hwirq/2) << 13) | CICR_HP_MASK);

	out_be32(&cpic_reg->cpic_cimr, 0);

	cpm_pic_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
				      64, &cpm_pic_host_ops, 64);
	if (cpm_pic_host == NULL) {
		printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
		sirq = NO_IRQ;
		goto end;
	}

	/* Install our own error handler. */
	np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
	if (np == NULL)
		np = of_find_node_by_type(NULL, "cpm");
	if (np == NULL) {
		printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
		goto end;
	}

	eirq = irq_of_parse_and_map(np, 0);
	if (eirq == NO_IRQ)
		goto end;

	if (setup_irq(eirq, &cpm_error_irqaction))
		printk(KERN_ERR "Could not allocate CPM error IRQ!");

	setbits32(&cpic_reg->cpic_cicr, CICR_IEN);

end:
	of_node_put(np);
	return sirq;
}

static void cpm_end_irq(struct irq_data *d)
{
	unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);

	out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
}

static inline void fifo_icap_fifo_write(struct hwicap_drvdata *drvdata,
		u32 data)
{
	dev_dbg(drvdata->dev, "fifo_write: %x\n", data);
	out_be32(drvdata->base_address + XHI_WF_OFFSET, data);
}

static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata,
		u32 data)
{
	out_be32(drvdata->base_address + XHI_SZ_OFFSET, data);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
		void *data_in, unsigned long flags)
{
	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
	ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
	unsigned int tmpdout, tmpdin, event;
	const void *dout = NULL;
	void *din = NULL;
	int len = 0;
	int num_blks, num_chunks, max_tran_len, tran_len;
	int num_bytes;
	unsigned char *ch;
	unsigned char *buffer = NULL;
	size_t buf_len;
	u8 *cmd_buf = fsl->cmd_buf;
	size_t cmd_len = fsl->cmd_len;
	size_t data_len = bitlen / 8;
	size_t rx_offset = 0;

	max_tran_len = fsl->max_transfer_length;
	switch (flags) {
	case SPI_XFER_BEGIN:
		cmd_len = fsl->cmd_len = data_len;
		memcpy(cmd_buf, data_out, cmd_len);
		return 0;
	case 0:
	case SPI_XFER_END:
		if (bitlen == 0) {
			spi_cs_deactivate(slave);
			return 0;
		}
		buf_len = 2 * cmd_len + min(data_len, max_tran_len);
		len = cmd_len + data_len;
		rx_offset = cmd_len;
		buffer = (unsigned char *)malloc(buf_len);
		if (!buffer) {
			debug("SF: Failed to malloc memory.\n");
			return 1;
		}
		memcpy(buffer, cmd_buf, cmd_len);
		if (cmd_len != 1) {
			if (data_in == NULL)
				memcpy(buffer + cmd_len, data_out, data_len);
		}
		break;
	case SPI_XFER_BEGIN | SPI_XFER_END:
		len = data_len;
		buffer = (unsigned char *)malloc(len * 2);
		if (!buffer) {
			debug("SF: Failed to malloc memory.\n");
			return 1;
		}
		memcpy(buffer, data_out, len);
		rx_offset = len;
		cmd_len = 0;
		break;
	}

	debug("spi_xfer: slave %u:%u dout %08X(%08x) din %08X(%08x) len %u\n",
	      slave->bus, slave->cs, *(uint *) dout,
	      dout, *(uint *) din, din, len);

	num_chunks = data_len / max_tran_len +
		(data_len % max_tran_len ? 1 : 0);
	while (num_chunks--) {
		if (data_in)
			din = buffer + rx_offset;
		dout = buffer;
		tran_len = min(data_len , max_tran_len);
		num_blks = (tran_len + cmd_len) / 4 +
			((tran_len + cmd_len) % 4 ? 1 : 0);
		num_bytes = (tran_len + cmd_len) % 4;
		fsl->data_len = tran_len + cmd_len;
		spi_cs_activate(slave);

		/* Clear all eSPI events */
		out_be32(&espi->event , 0xffffffff);
		/* handle data in 32-bit chunks */
		while (num_blks--) {

			event = in_be32(&espi->event);
			if (event & ESPI_EV_TNF) {
				tmpdout = *(u32 *)dout;

				/* Set up the next iteration */
				if (len > 4) {
					len -= 4;
					dout += 4;
				}

				out_be32(&espi->tx, tmpdout);
				out_be32(&espi->event, ESPI_EV_TNF);
				debug("***spi_xfer:...%08x written\n", tmpdout);
			}

			/* Wait for eSPI transmit to get out */
			udelay(80);

			event = in_be32(&espi->event);
			if (event & ESPI_EV_RNE) {
//.........这里部分代码省略.........

inline void ll_temac_xlplb_out32(phys_addr_t addr, unsigned value)
{
	out_be32((void *)addr, value);
}

int misc_init_r(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;

	/*
	 * Re-configure flash setup using auto-detected info
	 */
	if (flash_info[1].size > 0) {
		out_be32(&im->sysconf.lpcs1aw,
			CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
			CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
				  flash_info[1].size));
		sync_law(&im->sysconf.lpcs1aw);
		/*
		 * Re-check to get correct base address
		 */
		flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
	} else {
		/* Disable Bank 1 */
		out_be32(&im->sysconf.lpcs1aw, 0x01000100);
		sync_law(&im->sysconf.lpcs1aw);
	}

	out_be32(&im->sysconf.lpcs0aw,
		CSAW_START(gd->bd->bi_flashstart) |
		CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
	sync_law(&im->sysconf.lpcs0aw);

	/*
	 * Re-check to get correct base address
	 */
	flash_get_size (gd->bd->bi_flashstart, 0);

	/*
	 * Re-do flash protection upon new addresses
	 */
	flash_protect (FLAG_PROTECT_CLEAR,
		       gd->bd->bi_flashstart, 0xffffffff,
		       &flash_info[0]);

	/* Monitor protection ON by default */
	flash_protect (FLAG_PROTECT_SET,
		       CONFIG_SYS_MONITOR_BASE,
		       CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
		       &flash_info[0]);

	/* Environment protection ON by default */
	flash_protect (FLAG_PROTECT_SET,
		       CONFIG_ENV_ADDR,
		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
		       &flash_info[0]);

#ifdef CONFIG_ENV_ADDR_REDUND
	/* Redundant environment protection ON by default */
	flash_protect (FLAG_PROTECT_SET,
		       CONFIG_ENV_ADDR_REDUND,
		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
		       &flash_info[0]);
#endif

#ifdef CONFIG_FSL_DIU_FB
	set_lcd_brightness(0);
	/* Switch LCD-Backlight and LVDS-Interface on */
	setbits_be32(&im->gpio.gpdir, 0x01040000);
	clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
#endif

#if defined(CONFIG_HARD_I2C)
	if (!getenv("ethaddr")) {
		uchar buf[6];
		uchar ifm_oui[3] = { 0, 2, 1, };
		int ret;

		/* I2C-0 for on-board eeprom */
		i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);

		/* Read ethaddr from EEPROM */
		ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
			       CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
		if (ret != 0) {
			printf("Error: Unable to read MAC from I2C"
				" EEPROM at address %02X:%02X\n",
				CONFIG_SYS_I2C_EEPROM_ADDR,
				CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
			return 1;
		}

		/* Owned by IFM ? */
		if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
			printf("Illegal MAC address in EEPROM: %pM\n", buf);
			return 1;
		}

		eth_setenv_enetaddr("ethaddr", buf);
	}
#endif /* defined(CONFIG_HARD_I2C) */

	return 0;
}

void __init init_IRQ(void)
{
	u32 i, j, intr_type;
	struct device_node *intc = NULL;
#ifdef CONFIG_SELFMOD_INTC
	unsigned int intc_baseaddr = 0;
	static int arr_func[] = {
				(int)&get_irq,
				(int)&intc_enable_or_unmask,
				(int)&intc_disable_or_mask,
				(int)&intc_mask_ack,
				(int)&intc_ack,
				(int)&intc_end,
				0
			};
#endif
	const char * const intc_list[] = {
				"xlnx,xps-intc-1.00.a",
				NULL
			};

	for (j = 0; intc_list[j] != NULL; j++) {
		intc = of_find_compatible_node(NULL, NULL, intc_list[j]);
		if (intc)
			break;
	}
	BUG_ON(!intc);

	intc_baseaddr = be32_to_cpup(of_get_property(intc,
								"reg", NULL));
	intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
	nr_irq = be32_to_cpup(of_get_property(intc,
						"xlnx,num-intr-inputs", NULL));

	intr_type =
		be32_to_cpup(of_get_property(intc,
						"xlnx,kind-of-intr", NULL));
	if (intr_type >= (1 << (nr_irq + 1)))
		printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");

#ifdef CONFIG_SELFMOD_INTC
	selfmod_function((int *) arr_func, intc_baseaddr);
#endif
	printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
		intc_list[j], intc_baseaddr, nr_irq, intr_type);

	/*
	 * Disable all external interrupts until they are
	 * explicity requested.
	 */
	out_be32(intc_baseaddr + IER, 0);

	/* Acknowledge any pending interrupts just in case. */
	out_be32(intc_baseaddr + IAR, 0xffffffff);

	/* Turn on the Master Enable. */
	out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);

	for (i = 0; i < nr_irq; ++i) {
		if (intr_type & (0x00000001 << i)) {
			irq_set_chip_and_handler_name(i, &intc_dev,
				handle_edge_irq, "edge");
			irq_clear_status_flags(i, IRQ_LEVEL);
		} else {
			irq_set_chip_and_handler_name(i, &intc_dev,
				handle_level_irq, "level");
			irq_set_status_flags(i, IRQ_LEVEL);
		}
	}
}

static void intc_ack(struct irq_data *d)
{
	pr_debug("ack: %d\n", d->irq);
	out_be32(INTC_BASE + IAR, 1 << d->irq);
}

static int __devinit
bcom_engine_init(void)
{
    int task;
    phys_addr_t tdt_pa, ctx_pa, var_pa, fdt_pa;
    unsigned int tdt_size, ctx_size, var_size, fdt_size;
    u16 regval;

    /* Allocate & clear SRAM zones for FDT, TDTs, contexts and vars/incs */
    tdt_size = BCOM_MAX_TASKS * sizeof(struct bcom_tdt);
    ctx_size = BCOM_MAX_TASKS * BCOM_CTX_SIZE;
    var_size = BCOM_MAX_TASKS * (BCOM_VAR_SIZE + BCOM_INC_SIZE);
    fdt_size = BCOM_FDT_SIZE;

    bcom_eng->tdt = bcom_sram_alloc(tdt_size, sizeof(u32), &tdt_pa);
    bcom_eng->ctx = bcom_sram_alloc(ctx_size, BCOM_CTX_ALIGN, &ctx_pa);
    bcom_eng->var = bcom_sram_alloc(var_size, BCOM_VAR_ALIGN, &var_pa);
    bcom_eng->fdt = bcom_sram_alloc(fdt_size, BCOM_FDT_ALIGN, &fdt_pa);

    if (!bcom_eng->tdt || !bcom_eng->ctx || !bcom_eng->var || !bcom_eng->fdt) {
        printk(KERN_ERR "DMA: SRAM alloc failed in engine init !\n");

        bcom_sram_free(bcom_eng->tdt);
        bcom_sram_free(bcom_eng->ctx);
        bcom_sram_free(bcom_eng->var);
        bcom_sram_free(bcom_eng->fdt);

        return -ENOMEM;
    }

    memset(bcom_eng->tdt, 0x00, tdt_size);
    memset(bcom_eng->ctx, 0x00, ctx_size);
    memset(bcom_eng->var, 0x00, var_size);
    memset(bcom_eng->fdt, 0x00, fdt_size);

    /* Copy the FDT for the EU#3 */
    memcpy(&bcom_eng->fdt[48], fdt_ops, sizeof(fdt_ops));

    /* Initialize Task base structure */
    for (task=0; task<BCOM_MAX_TASKS; task++)
    {
        out_be16(&bcom_eng->regs->tcr[task], 0);
        out_8(&bcom_eng->regs->ipr[task], 0);

        bcom_eng->tdt[task].context    = ctx_pa;
        bcom_eng->tdt[task].var    = var_pa;
        bcom_eng->tdt[task].fdt    = fdt_pa;

        var_pa += BCOM_VAR_SIZE + BCOM_INC_SIZE;
        ctx_pa += BCOM_CTX_SIZE;
    }

    out_be32(&bcom_eng->regs->taskBar, tdt_pa);

    /* Init 'always' initiator */
    out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ALWAYS], BCOM_IPR_ALWAYS);

    /* Disable COMM Bus Prefetch on the original 5200; it's broken */
    if ((mfspr(SPRN_SVR) & MPC5200_SVR_MASK) == MPC5200_SVR) {
        regval = in_be16(&bcom_eng->regs->PtdCntrl);
        out_be16(&bcom_eng->regs->PtdCntrl,  regval | 1);
    }

    /* Init lock */
    spin_lock_init(&bcom_eng->lock);

    return 0;
}

static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata)
{
	out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_WRITE_MASK);
	dev_dbg(drvdata->dev, "configuration started\n");
}

void ddrmc_init(void)
{
	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
	u32 temp_sdram_cfg;

	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);

	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);

	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);

#ifdef CONFIG_DEEP_SLEEP
	if (is_warm_boot()) {
		out_be32(&ddr->sdram_cfg_2,
			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
		out_be32(&ddr->init_ext_addr, (1 << 31));

		/* DRAM VRef will not be trained */
		out_be32(&ddr->ddr_cdr2,
			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
	} else
#endif
	{
		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
	}

	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);

	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);

	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);

	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);

	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);

	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);

	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
	udelay(1);

#ifdef CONFIG_DEEP_SLEEP
	if (is_warm_boot()) {
		/* enter self-refresh */
		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);

		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
	} else
#endif
		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);

	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);

#ifdef CONFIG_DEEP_SLEEP
	if (is_warm_boot()) {
		/* exit self-refresh */
		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
	}
#endif
}

static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata)
{
	out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_READ_MASK);
	dev_dbg(drvdata->dev, "readback started\n");
}

//.........这里部分代码省略.........
		{CPM_CLK_SCC3, CPM_BRG3, 2},
		{CPM_CLK_SCC3, CPM_BRG4, 3},
		{CPM_CLK_SCC3, CPM_CLK5, 4},
		{CPM_CLK_SCC3, CPM_CLK6, 5},
		{CPM_CLK_SCC3, CPM_CLK7, 6},
		{CPM_CLK_SCC3, CPM_CLK8, 7},

		{CPM_CLK_SCC4, CPM_BRG1, 0},
		{CPM_CLK_SCC4, CPM_BRG2, 1},
		{CPM_CLK_SCC4, CPM_BRG3, 2},
		{CPM_CLK_SCC4, CPM_BRG4, 3},
		{CPM_CLK_SCC4, CPM_CLK5, 4},
		{CPM_CLK_SCC4, CPM_CLK6, 5},
		{CPM_CLK_SCC4, CPM_CLK7, 6},
		{CPM_CLK_SCC4, CPM_CLK8, 7},

		{CPM_CLK_SMC1, CPM_BRG1, 0},
		{CPM_CLK_SMC1, CPM_BRG2, 1},
		{CPM_CLK_SMC1, CPM_BRG3, 2},
		{CPM_CLK_SMC1, CPM_BRG4, 3},
		{CPM_CLK_SMC1, CPM_CLK1, 4},
		{CPM_CLK_SMC1, CPM_CLK2, 5},
		{CPM_CLK_SMC1, CPM_CLK3, 6},
		{CPM_CLK_SMC1, CPM_CLK4, 7},

		{CPM_CLK_SMC2, CPM_BRG1, 0},
		{CPM_CLK_SMC2, CPM_BRG2, 1},
		{CPM_CLK_SMC2, CPM_BRG3, 2},
		{CPM_CLK_SMC2, CPM_BRG4, 3},
		{CPM_CLK_SMC2, CPM_CLK5, 4},
		{CPM_CLK_SMC2, CPM_CLK6, 5},
		{CPM_CLK_SMC2, CPM_CLK7, 6},
		{CPM_CLK_SMC2, CPM_CLK8, 7},
	};

	switch (target) {
	case CPM_CLK_SCC1:
		reg = &mpc8xx_immr->im_cpm.cp_sicr;
		shift = 0;
		break;

	case CPM_CLK_SCC2:
		reg = &mpc8xx_immr->im_cpm.cp_sicr;
		shift = 8;
		break;

	case CPM_CLK_SCC3:
		reg = &mpc8xx_immr->im_cpm.cp_sicr;
		shift = 16;
		break;

	case CPM_CLK_SCC4:
		reg = &mpc8xx_immr->im_cpm.cp_sicr;
		shift = 24;
		break;

	case CPM_CLK_SMC1:
		reg = &mpc8xx_immr->im_cpm.cp_simode;
		shift = 12;
		break;

	case CPM_CLK_SMC2:
		reg = &mpc8xx_immr->im_cpm.cp_simode;
		shift = 28;
		break;

	default:
		printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
		return -EINVAL;
	}

	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
			bits = clk_map[i][2];
			break;
		}
	}

	if (i == ARRAY_SIZE(clk_map)) {
		printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
		return -EINVAL;
	}

	bits <<= shift;
	mask <<= shift;

	if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
		if (mode == CPM_CLK_RTX) {
			bits |= bits << 3;
			mask |= mask << 3;
		} else if (mode == CPM_CLK_RX) {
			bits <<= 3;
			mask <<= 3;
		}
	}

	out_be32(reg, (in_be32(reg) & ~mask) | bits);

	return 0;
}

int ads5121_fuse_sense(int bank, int fstart, int num)
{
	iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
	u32 iim_fbac;
	u32 stat, err, err_hold = 0;
	int f, ctr;

	out_be32(&iim->err, in_be32(&iim->err));
	if (bank == 0)
		iim_fbac = in_be32(&iim->fbac0);
	else
		iim_fbac = in_be32(&iim->fbac1);
	if (iim_fbac & IIM_FBAC_FBESP) {
		printf("\tSense Protect disallows this operation\n");
		out_be32(&iim->err, IIM_FBAC_FBESP);
		return 1;
	}
	err = in_be32(&iim->err);
	if (err) {
		iim_err_msg(err);
		err_hold |= err;
	}
	if (err & IIM_ERR_RPE)
		printf("\tRead protect fuse is set; "
			"Sense Protect may be set but will be attempted\n");
	if (err)
		out_be32(&iim->err, err);
	printf("Sensing fuse(s) on Bank %d\n", bank);
	for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) {
		out_be32(&iim->ua, IIM_SET_UA(bank, f));
		out_be32(&iim->la, IIM_SET_LA(f, 0));
		out_be32(&iim->fctl,  IIM_FCTL_ESNS_N);
		do
			udelay(20);
		while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
		err = in_be32(&iim->err);
		if (err & IIM_ERR_SNSE) {
			iim_err_msg(err);
			out_be32(&iim->err, IIM_ERR_SNSE);
			return 1;
		}
		if (stat & IIM_STAT_SNSD) {
			out_be32(&iim->stat, 0);
			if (ctr % 4 == 0)
				printf("F%2d:", f);
			printf("\t%#04x", (u8)iim->sdat);
			if (ctr % 4 == 3)
				printf("\n");
		}
		if (err) {
			err_hold |= err;
			out_be32(&iim->err, err);
		}
	}
	if (ctr % 4 != 0)
		printf("\n");
	if (err_hold)
		iim_err_msg(err_hold);

	return 0;
}