STDCALL void WRAP_EXPORT(WRITE_PORT_USHORT)
	(ULONG_PTR port, USHORT value)
{
	outw(value, port);
}

static inline void
mikasa_update_irq_hw(int mask)
{
	outw(mask, 0x536);
}

static inline void
Write_hfc16(hfc4s8s_hw * a, u_char b, u_short c)
{
	SetRegAddr(a, b);
	outw(c, a->iobase);
}

static void vx800_writesioword(uint16_t reg, uint16_t val)
{
	outw(val, reg);
}

__initfunc(static int seeq8005_probe1(struct device *dev, int ioaddr))
{
	static unsigned version_printed = 0;
	int i,j;
	unsigned char SA_prom[32];
	int old_cfg1;
	int old_cfg2;
	int old_stat;
	int old_dmaar;
	int old_rear;

	if (net_debug>1)
		printk("seeq8005: probing at 0x%x\n",ioaddr);

	old_stat = inw(SEEQ_STATUS);					/* read status register */
	if (old_stat == 0xffff)
		return ENODEV;						/* assume that 0xffff == no device */
	if ( (old_stat & 0x1800) != 0x1800 ) {				/* assume that unused bits are 1, as my manual says */
		if (net_debug>1) {
			printk("seeq8005: reserved stat bits != 0x1800\n");
			printk("          == 0x%04x\n",old_stat);
		}
	 	return ENODEV;
	}

	old_rear = inw(SEEQ_REA);
	if (old_rear == 0xffff) {
		outw(0,SEEQ_REA);
		if (inw(SEEQ_REA) == 0xffff) {				/* assume that 0xffff == no device */
			return ENODEV;
		}
	} else if ((old_rear & 0xff00) != 0xff00) {			/* assume that unused bits are 1 */
		if (net_debug>1) {
			printk("seeq8005: unused rear bits != 0xff00\n");
			printk("          == 0x%04x\n",old_rear);
		}
		return ENODEV;
	}
	
	old_cfg2 = inw(SEEQ_CFG2);					/* read CFG2 register */
	old_cfg1 = inw(SEEQ_CFG1);
	old_dmaar = inw(SEEQ_DMAAR);
	
	if (net_debug>4) {
		printk("seeq8005: stat = 0x%04x\n",old_stat);
		printk("seeq8005: cfg1 = 0x%04x\n",old_cfg1);
		printk("seeq8005: cfg2 = 0x%04x\n",old_cfg2);
		printk("seeq8005: raer = 0x%04x\n",old_rear);
		printk("seeq8005: dmaar= 0x%04x\n",old_dmaar);
	}
	
	outw( SEEQCMD_FIFO_WRITE | SEEQCMD_SET_ALL_OFF, SEEQ_CMD);	/* setup for reading PROM */
	outw( 0, SEEQ_DMAAR);						/* set starting PROM address */
	outw( SEEQCFG1_BUFFER_PROM, SEEQ_CFG1);				/* set buffer to look at PROM */
	
	
	j=0;
	for(i=0; i <32; i++) {
		j+= SA_prom[i] = inw(SEEQ_BUFFER) & 0xff;
	}

#if 0
	/* untested because I only have the one card */
	if ( (j&0xff) != 0 ) {						/* checksum appears to be 8bit = 0 */
		if (net_debug>1) {					/* check this before deciding that we have a card */
			printk("seeq8005: prom sum error\n");
		}
		outw( old_stat, SEEQ_STATUS);
		outw( old_dmaar, SEEQ_DMAAR);
		outw( old_cfg1, SEEQ_CFG1);
		return ENODEV;
	}
#endif

	outw( SEEQCFG2_RESET, SEEQ_CFG2);				/* reset the card */
	udelay(5);
	outw( SEEQCMD_SET_ALL_OFF, SEEQ_CMD);
	
	if (net_debug) {
		printk("seeq8005: prom sum = 0x%08x\n",j);
		for(j=0; j<32; j+=16) {
			printk("seeq8005: prom %02x: ",j);
			for(i=0;i<16;i++) {
				printk("%02x ",SA_prom[j|i]);
			}
			printk(" ");
			for(i=0;i<16;i++) {
				if ((SA_prom[j|i]>31)&&(SA_prom[j|i]<127)) {
					printk("%c", SA_prom[j|i]);
				} else {
					printk(" ");
				}
			}
			printk("\n");
		}
	}

#if 0	
	/* 
	 * testing the packet buffer memory doesn't work yet
//.........这里部分代码省略.........

static void
eesoxscsi_dma_pseudo(struct Scsi_Host *host, Scsi_Pointer *SCp,
		     fasdmadir_t dir, int transfer_size)
{
	EESOXScsi_Info *info = (EESOXScsi_Info *)host->hostdata;
	unsigned int status;
	unsigned int length = SCp->this_residual;
	union {
		unsigned char *c;
		unsigned short *s;
		unsigned long *l;
	} buffer;

	buffer.c = SCp->ptr;

	status = inb(host->io_port + EESOX_STATUS);
	if (dir == DMA_IN) {
		while (length > 8) {
			if (status & EESOX_STAT_DMA) {
				unsigned long l1, l2;

				l1 = inw(info->dmaarea);
				l1 |= inw(info->dmaarea) << 16;
				l2 = inw(info->dmaarea);
				l2 |= inw(info->dmaarea) << 16;
				*buffer.l++ = l1;
				*buffer.l++ = l2;
				length -= 8;
			} else if (status & EESOX_STAT_INTR)
				goto end;
			status = inb(host->io_port + EESOX_STATUS);
		}

		while (length > 1) {
			if (status & EESOX_STAT_DMA) {
				*buffer.s++ = inw(info->dmaarea);
				length -= 2;
			} else if (status & EESOX_STAT_INTR)
				goto end;
			status = inb(host->io_port + EESOX_STATUS);
		}

		while (length > 0) {
			if (status & EESOX_STAT_DMA) {
				*buffer.c++ = inw(info->dmaarea);
				length -= 1;
			} else if (status & EESOX_STAT_INTR)
				goto end;
			status = inb(host->io_port + EESOX_STATUS);
		}
	} else {
		while (length > 8) {
			if (status & EESOX_STAT_DMA) {
				unsigned long l1, l2;

				l1 = *buffer.l++;
				l2 = *buffer.l++;

				outw(l1, info->dmaarea);
				outw(l1 >> 16, info->dmaarea);
				outw(l2, info->dmaarea);
				outw(l2 >> 16, info->dmaarea);
				length -= 8;
			} else if (status & EESOX_STAT_INTR)
				goto end;
			status = inb(host->io_port + EESOX_STATUS);
		}

int
system_call_implementation(void)
{
 register int schedule=0;
 /*!< System calls may set this variable to 1. The variable is used as
      input to the scheduler to indicate if scheduling is necessary. */
 switch(SYSCALL_ARGUMENTS.rax)
 {
  case SYSCALL_PRINTS:
  {
   kprints((char*) (SYSCALL_ARGUMENTS.rdi));
   SYSCALL_ARGUMENTS.rax = ALL_OK;

   break;
  }

  case SYSCALL_PRINTHEX:
  {
   kprinthex(SYSCALL_ARGUMENTS.rdi);
   SYSCALL_ARGUMENTS.rax = ALL_OK;
   break;
  }

  case SYSCALL_DEBUGGER:
  {
   /* Enable the bochs iodevice and force a return to the debugger. */
   outw(0x8a00, 0x8a00);
   outw(0x8a00, 0x8ae0);

   SYSCALL_ARGUMENTS.rax = ALL_OK;
   break;
  }

	case SYSCALL_VERSION: {
		SYSCALL_ARGUMENTS.rax = KERNEL_VERSION;
		break;
	}

	case SYSCALL_CREATEPROCESS: {

		int process_number, thread_number;
		long int executable_number = SYSCALL_ARGUMENTS.rdi;
		struct prepare_process_return_value prepare_process_ret_val;


		for (process_number = 0; process_number < MAX_NUMBER_OF_PROCESSES && process_table[process_number].threads > 0; process_number++) {
		}
		prepare_process_ret_val = prepare_process(
				executable_table[executable_number].elf_image,
				process_number,
				executable_table[executable_number].memory_footprint_size);

		if(0 == prepare_process_ret_val.first_instruction_address) {
			kprints("Error starting image\n");
		}

		process_table[process_number].parent = thread_table[cpu_private_data.thread_index].data.owner;

		thread_number = allocate_thread();

		thread_table[thread_number].data.owner = process_number;
		thread_table[thread_number].data.registers.integer_registers.rflags = 0x200;
		thread_table[thread_number].data.registers.integer_registers.rip = prepare_process_ret_val.first_instruction_address;

		process_table[process_number].threads += 1;

		SYSCALL_ARGUMENTS.rax = ALL_OK;

		thread_queue_enqueue(&ready_queue,thread_number);
		/*cpu_private_data.thread_index = thread_number;*/


		break;
	}
	case SYSCALL_TERMINATE:
	{
		int i;
		int owner_process = thread_table[cpu_private_data.thread_index].data.owner;
		int parent_process = process_table[owner_process].parent;

		thread_table[cpu_private_data.thread_index].data.owner = -1; /* Terminate Thread */

		process_table[owner_process].threads -= 1; /* Decrement Thread count */

		if(process_table[owner_process].threads < 1) {
			cleanup_process(owner_process);
		}

		for(i=0; i < MAX_NUMBER_OF_THREADS && thread_table[i].data.owner != parent_process; i++) {
		}

		/*cpu_private_data.thread_index = i;*/
		/*thread_queue_dequeue(&ready_queue);*/
		schedule = 1;

		break;

	}


//.........这里部分代码省略.........

static int me8100_di_io_irq_start(me_subdevice_t *subdevice,
				  struct file *filep,
				  int channel,
				  int irq_source,
				  int irq_edge, int irq_arg, int flags)
{
	me8100_di_subdevice_t *instance;
	int err = ME_ERRNO_SUCCESS;
	uint16_t ctrl;
	unsigned long cpu_flags;

	PDEBUG("executed.\n");

	instance = (me8100_di_subdevice_t *) subdevice;

	if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
		if (flags &
		    ~(ME_IO_IRQ_START_PATTERN_FILTERING |
		      ME_IO_IRQ_START_DIO_WORD)) {
			PERROR("Invalid flag specified.\n");
			return ME_ERRNO_INVALID_FLAGS;
		}

		if (irq_edge != ME_IRQ_EDGE_NOT_USED) {
			PERROR("Invalid irq edge specified.\n");
			return ME_ERRNO_INVALID_IRQ_EDGE;
		}
	} else if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
		if (flags &
		    ~(ME_IO_IRQ_START_EXTENDED_STATUS |
		      ME_IO_IRQ_START_DIO_WORD)) {
			PERROR("Invalid flag specified.\n");
			return ME_ERRNO_INVALID_FLAGS;
		}

		if (irq_edge != ME_IRQ_EDGE_ANY) {
			PERROR("Invalid irq edge specified.\n");
			return ME_ERRNO_INVALID_IRQ_EDGE;
		}

		if (!(irq_arg & 0xFFFF)) {
			PERROR("No mask specified.\n");
			return ME_ERRNO_INVALID_IRQ_ARG;
		}
	} else {
		PERROR("Invalid irq source specified.\n");
		return ME_ERRNO_INVALID_IRQ_SOURCE;
	}

	if (channel) {
		PERROR("Invalid channel specified.\n");
		return ME_ERRNO_INVALID_CHANNEL;
	}

	ME_SUBDEVICE_ENTER;

	spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
	if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
		outw(irq_arg, instance->pattern_reg);
		instance->compare_value = irq_arg;
		instance->filtering_flag =
		    (flags & ME_IO_IRQ_START_PATTERN_FILTERING) ? 1 : 0;
	}
	if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
		outw(irq_arg, instance->mask_reg);
	}

	spin_lock(instance->ctrl_reg_lock);
	ctrl = inw(instance->ctrl_reg);
	ctrl |= ME8100_DIO_CTRL_BIT_INTB_0;
	if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
		ctrl &= ~ME8100_DIO_CTRL_BIT_INTB_1;
	}

	if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
		ctrl |= ME8100_DIO_CTRL_BIT_INTB_1;
	}
	outw(ctrl, instance->ctrl_reg);
	PDEBUG_REG("ctrl_reg outw(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
		   instance->ctrl_reg - instance->reg_base, ctrl);
	spin_unlock(instance->ctrl_reg_lock);

	instance->rised = 0;
	instance->status_value = 0;
	instance->status_value_edges = 0;
	instance->line_value = inw(instance->port_reg);
	instance->status_flag = flags & ME_IO_IRQ_START_EXTENDED_STATUS;
	spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);

	ME_SUBDEVICE_EXIT;

	return err;
}

static struct sal_ret_values
sal_emulator (long index, unsigned long in1, unsigned long in2,
	      unsigned long in3, unsigned long in4, unsigned long in5,
	      unsigned long in6, unsigned long in7)
{
	long r9  = 0;
	long r10 = 0;
	long r11 = 0;
	long status;

	/*
	 * Don't do a "switch" here since that gives us code that
	 * isn't self-relocatable.
	 */
	status = 0;
	if (index == SAL_FREQ_BASE) {
		if (in1 == SAL_FREQ_BASE_PLATFORM)
			r9 = 200000000;
		else if (in1 == SAL_FREQ_BASE_INTERVAL_TIMER) {
			/*
			 * Is this supposed to be the cr.itc frequency
			 * or something platform specific?  The SAL
			 * doc ain't exactly clear on this...
			 */
			r9 = 700000000;
		} else if (in1 == SAL_FREQ_BASE_REALTIME_CLOCK)
			r9 = 1;
		else
			status = -1;
	} else if (index == SAL_SET_VECTORS) {
		;
	} else if (index == SAL_GET_STATE_INFO) {
		;
	} else if (index == SAL_GET_STATE_INFO_SIZE) {
		;
	} else if (index == SAL_CLEAR_STATE_INFO) {
		;
	} else if (index == SAL_MC_RENDEZ) {
		;
	} else if (index == SAL_MC_SET_PARAMS) {
		;
	} else if (index == SAL_CACHE_FLUSH) {
		;
	} else if (index == SAL_CACHE_INIT) {
		;
#ifdef CONFIG_PCI
	} else if (index == SAL_PCI_CONFIG_READ) {
		/*
		 * in1 contains the PCI configuration address and in2
		 * the size of the read.  The value that is read is
		 * returned via the general register r9.
		 */
                outl(BUILD_CMD(in1), 0xCF8);
                if (in2 == 1)                           /* Reading byte  */
                        r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3)));
                else if (in2 == 2)                      /* Reading word  */
                        r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2)));
                else                                    /* Reading dword */
                        r9 = inl(0xCFC);
                status = PCIBIOS_SUCCESSFUL;
	} else if (index == SAL_PCI_CONFIG_WRITE) {
	      	/*
		 * in1 contains the PCI configuration address, in2 the
		 * size of the write, and in3 the actual value to be
		 * written out.
		 */
                outl(BUILD_CMD(in1), 0xCF8);
                if (in2 == 1)                           /* Writing byte  */
                        outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3)));
                else if (in2 == 2)                      /* Writing word  */
                        outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2)));
                else                                    /* Writing dword */
                        outl(in3, 0xCFC);
                status = PCIBIOS_SUCCESSFUL;
#endif /* CONFIG_PCI */
	} else if (index == SAL_UPDATE_PAL) {
		;
	} else {
		status = -1;
	}
	return ((struct sal_ret_values) {status, r9, r10, r11});

/* byte 1 and 2 is the port number to write
 * and at byte 3 the value to write starts.
 * I assume that there are and- and or- masks
 * here when HPEE_PORT_INIT_MASK is set but I have 
 * not yet encountered this. */
static int configure_port_init(const unsigned char *buf)
{
	int len=0;
	u_int8_t c;
	
	while (len<HPEE_PORT_INIT_MAX_LEN) {
		int s=0;
		c = get_8(buf+len);
		
		switch (c & HPEE_PORT_INIT_WIDTH_MASK)  {
		 case HPEE_PORT_INIT_WIDTH_BYTE:
			s=1;
			if (c & HPEE_PORT_INIT_MASK) {
				printk("\n" KERN_WARNING "port_init: unverified mask attribute\n");
				outb((inb(get_16(buf+len+1) & 
					  get_8(buf+len+3)) | 
				      get_8(buf+len+4)), get_16(buf+len+1));
				      
			} else {
				outb(get_8(buf+len+3), get_16(buf+len+1));
				      
			}
			break;
		 case HPEE_PORT_INIT_WIDTH_WORD:
			s=2;
			if (c & HPEE_PORT_INIT_MASK) {
 				printk(KERN_WARNING "port_init: unverified mask attribute\n");
				       outw((inw(get_16(buf+len+1)) &
					     get_16(buf+len+3)) |
					    get_16(buf+len+5), 
					    get_16(buf+len+1));
			} else {
				outw(cpu_to_le16(get_16(buf+len+3)), get_16(buf+len+1));
			}
			break;
		 case HPEE_PORT_INIT_WIDTH_DWORD:
			s=4;
			if (c & HPEE_PORT_INIT_MASK) {
 				printk("\n" KERN_WARNING "port_init: unverified mask attribute\n");
				outl((inl(get_16(buf+len+1) &
					  get_32(buf+len+3)) |
				      get_32(buf+len+7)), get_16(buf+len+1));
			} else {
				outl(cpu_to_le32(get_32(buf+len+3)), get_16(buf+len+1));
			}

			break;
		 default:
			printk("\n" KERN_ERR "Invalid port init word %02x\n", c);
			return 0;
		}
		
		if (c & HPEE_PORT_INIT_MASK) {   
			s*=2;
		}
		
		len+=s+3;
		if (!(c & HPEE_PORT_INIT_MORE)) {
			break;
		}
	}
	
	return len;
}

static void cx700_writesioword(u16 reg, u16 val)
{
	outw(val, reg);
}

void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value)
{
	outw(value, chip->addr + reg);
	chip->saved_registers._16[reg / 2] = cpu_to_le16(value);
}

void vbgfx_set_res(vga_card* v, int64_t w, int64_t h, uint8_t bpp)
{
  if(!v) return;
  if(!v->data[0]) return;
  if(w * h > 1440000) return;
  uint32_t iobase = v->data[0];
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_ENABLE);
  outw(iobase + VBGFX_IO_DATA, 0); //disable VBE extensions
  //write resolution
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_XRES);
  outw(iobase + VBGFX_IO_DATA, w);
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_YRES);
  outw(iobase + VBGFX_IO_DATA, h);
  //write bpp
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_BPP);
  outw(iobase + VBGFX_IO_DATA, bpp);
  //reset video module
  vdestroy();
  //enable VBE extensions and LFB
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_ENABLE);
  outw(iobase + VBGFX_IO_DATA, 1 | 0x40);
  //init video module
  int64_t width, height, bppix;
  uint32_t lfb_addr = pci_config_read_dword(v->bus, v->slot, 0, 0x10) & ~0xF;
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_XRES);
  width = inw(iobase + VBGFX_IO_DATA);
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_YRES);
  height = inw(iobase + VBGFX_IO_DATA);
  outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_BPP);
  bppix = inl(iobase + VBGFX_IO_DATA);
  vinit(width, height, bppix, w * 4, lfb_addr);
}

static void InitBoard(struct net_device *dev)
{
	ibmlana_priv *priv = netdev_priv(dev);
	int camcnt;
	camentry_t cams[16];
	u32 cammask;
	struct dev_mc_list *mcptr;
	u16 rcrval;

	/* reset the SONIC */

	outw(CMDREG_RST, dev->base_addr + SONIC_CMDREG);
	udelay(10);

	/* clear all spurious interrupts */

	outw(inw(dev->base_addr + SONIC_ISREG), dev->base_addr + SONIC_ISREG);

	/* set up the SONIC's bus interface - constant for this adapter -
	   must be done while the SONIC is in reset */

	outw(DCREG_USR1 | DCREG_USR0 | DCREG_WC1 | DCREG_DW32, dev->base_addr + SONIC_DCREG);
	outw(0, dev->base_addr + SONIC_DCREG2);

	/* remove reset form the SONIC */

	outw(0, dev->base_addr + SONIC_CMDREG);
	udelay(10);

	/* data sheet requires URRA to be programmed before setting up the CAM contents */

	outw(0, dev->base_addr + SONIC_URRA);

	/* program the CAM entry 0 to the device address */

	camcnt = 0;
	putcam(cams, &camcnt, dev->dev_addr);

	/* start putting the multicast addresses into the CAM list.  Stop if
	   it is full. */

	for (mcptr = dev->mc_list; mcptr != NULL; mcptr = mcptr->next) {
		putcam(cams, &camcnt, mcptr->dmi_addr);
		if (camcnt == 16)
			break;
	}

	/* calculate CAM mask */

	cammask = (1 << camcnt) - 1;

	/* feed CDA into SONIC, initialize RCR value (always get broadcasts) */

	memcpy_toio(priv->base, cams, sizeof(camentry_t) * camcnt);
	memcpy_toio(priv->base + (sizeof(camentry_t) * camcnt), &cammask, sizeof(cammask));

#ifdef DEBUG
	printk("CAM setup:\n");
	dumpmem(dev, 0, sizeof(camentry_t) * camcnt + sizeof(cammask));
#endif

	outw(0, dev->base_addr + SONIC_CAMPTR);
	outw(camcnt, dev->base_addr + SONIC_CAMCNT);
	outw(CMDREG_LCAM, dev->base_addr + SONIC_CMDREG);
	if (!wait_timeout(dev, SONIC_CMDREG, CMDREG_LCAM, 0, 2)) {
		printk(KERN_ERR "%s:SONIC did not respond on LCAM command - giving up.", dev->name);
		return;
	} else {
		/* clear interrupt condition */

		outw(ISREG_LCD, dev->base_addr + SONIC_ISREG);

#ifdef DEBUG
		printk("Loading CAM done, address pointers %04x:%04x\n",
		       inw(dev->base_addr + SONIC_URRA),
		       inw(dev->base_addr + SONIC_CAMPTR));
		{
			int z;

			printk("\n-->CAM: PTR %04x CNT %04x\n",
			       inw(dev->base_addr + SONIC_CAMPTR),
			       inw(dev->base_addr + SONIC_CAMCNT));
			outw(CMDREG_RST, dev->base_addr + SONIC_CMDREG);
			for (z = 0; z < camcnt; z++) {
				outw(z, dev->base_addr + SONIC_CAMEPTR);
				printk("Entry %d: %04x %04x %04x\n", z,
				       inw(dev->base_addr + SONIC_CAMADDR0),
				       inw(dev->base_addr + SONIC_CAMADDR1),
				       inw(dev->base_addr + SONIC_CAMADDR2));
			}
			outw(0, dev->base_addr + SONIC_CMDREG);
		}
#endif
	}

	rcrval = RCREG_BRD | RCREG_LB_NONE;

	/* if still multicast addresses left or ALLMULTI is set, set the multicast
	   enable bit */

//.........这里部分代码省略.........

/* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list
   of available transceivers.  */
void t21142_timer(unsigned long data)
{
#if 0
	/*RTnet*/struct rtnet_device *rtdev = (/*RTnet*/struct rtnet_device *)data;
	struct tulip_private *tp = (struct tulip_private *)rtdev->priv;
	long ioaddr = rtdev->base_addr;
	int csr12 = inl(ioaddr + CSR12);
	int next_tick = 60*HZ;
	int new_csr6 = 0;

	if (tulip_debug > 2)
		/*RTnet*/rtdm_printk(KERN_INFO"%s: 21143 negotiation status %8.8x, %s.\n",
			   rtdev->name, csr12, medianame[rtdev->if_port]);
	if (tulip_media_cap[rtdev->if_port] & MediaIsMII) {
		tulip_check_duplex(dev);
		next_tick = 60*HZ;
	} else if (tp->nwayset) {
		/* Don't screw up a negotiated session! */
		if (tulip_debug > 1)
			/*RTnet*/rtdm_printk(KERN_INFO"%s: Using NWay-set %s media, csr12 %8.8x.\n",
				   rtdev->name, medianame[rtdev->if_port], csr12);
	} else if (tp->medialock) {
			;
	} else if (rtdev->if_port == 3) {
		if (csr12 & 2) {	/* No 100mbps link beat, revert to 10mbps. */
			if (tulip_debug > 1)
				/*RTnet*/rtdm_printk(KERN_INFO"%s: No 21143 100baseTx link beat, %8.8x, "
					   "trying NWay.\n", rtdev->name, csr12);
			t21142_start_nway(dev);
			next_tick = 3*HZ;
		}
	} else if ((csr12 & 0x7000) != 0x5000) {
		/* Negotiation failed.  Search media types. */
		if (tulip_debug > 1)
			/*RTnet*/rtdm_printk(KERN_INFO"%s: 21143 negotiation failed, status %8.8x.\n",
				   rtdev->name, csr12);
		if (!(csr12 & 4)) {		/* 10mbps link beat good. */
			new_csr6 = 0x82420000;
			rtdev->if_port = 0;
			outl(0, ioaddr + CSR13);
			outl(0x0003FFFF, ioaddr + CSR14);
			outw(t21142_csr15[rtdev->if_port], ioaddr + CSR15);
			outl(t21142_csr13[rtdev->if_port], ioaddr + CSR13);
		} else {
			/* Select 100mbps port to check for link beat. */
			new_csr6 = 0x83860000;
			rtdev->if_port = 3;
			outl(0, ioaddr + CSR13);
			outl(0x0003FF7F, ioaddr + CSR14);
			outw(8, ioaddr + CSR15);
			outl(1, ioaddr + CSR13);
		}
		if (tulip_debug > 1)
			/*RTnet*/rtdm_printk(KERN_INFO"%s: Testing new 21143 media %s.\n",
				   rtdev->name, medianame[rtdev->if_port]);
		if (new_csr6 != (tp->csr6 & ~0x00D5)) {
			tp->csr6 &= 0x00D5;
			tp->csr6 |= new_csr6;
			outl(0x0301, ioaddr + CSR12);
			tulip_restart_rxtx(tp);
		}
		next_tick = 3*HZ;
	}

	/* mod_timer synchronizes us with potential add_timer calls
	 * from interrupts.
	 */
	/*RTnet*/MUST_REMOVE_mod_timer(&tp->timer, RUN_AT(next_tick));
#endif
}

void led_set_state(unsigned short value)
{
	outw(value & 0xFF, LED_BASE);
}

static inline void outw_data(unsigned int val, unsigned int base_addr)
{
	outw(val, base_addr + PORT_DATA);
}

static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
{
	outw(data, reg);
	pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
}

//.........这里部分代码省略.........
	mem = ioremap(phymem, PCI_SIZE);
	if ( mem == 0 ) {
		WLAN_LOG_ERROR("%s: ioremap() failed.\n", dev_info);
		result = -EIO;
		goto fail;
	}

	/* Log the device */
        WLAN_LOG_INFO("A Prism2.5 PCI device found, "
		"phymem:0x%llx, irq:%d, mem:0x%p\n", 
		(unsigned long long)phymem, pdev->irq, mem);
	
	if ((wlandev = create_wlan()) == NULL) {
		WLAN_LOG_ERROR("%s: Memory allocation failure.\n", dev_info);
		result = -EIO;
		goto fail;
	}
	hw = wlandev->priv;
	
	if ( wlan_setup(wlandev) != 0 ) {
		WLAN_LOG_ERROR("%s: wlan_setup() failed.\n", dev_info);
		result = -EIO;
		goto fail;
	}

	/* Setup netdevice's ability to report resources 
	 * Note: the netdevice was allocated by wlan_setup()
	 */
        wlandev->netdev->irq = pdev->irq;
        wlandev->netdev->mem_start = (unsigned long) mem;
        wlandev->netdev->mem_end = wlandev->netdev->mem_start + 
		pci_resource_len(pdev, 0);

	/* Register the wlandev, this gets us a name and registers the
	 * linux netdevice.
	 */
	SET_MODULE_OWNER(wlandev->netdev);
        if ( register_wlandev(wlandev) != 0 ) {
		WLAN_LOG_ERROR("%s: register_wlandev() failed.\n", dev_info);
		result = -EIO;
		goto fail;
        }

#if 0
	/* TODO: Move this and an irq test into an hfa384x_testif() routine.
	 */
	outw(PRISM2STA_MAGIC, HFA384x_SWSUPPORT(wlandev->netdev->base_addr));
	reg=inw( HFA384x_SWSUPPORT(wlandev->netdev->base_addr));
	if ( reg != PRISM2STA_MAGIC ) {
		WLAN_LOG_ERROR("MAC register access test failed!\n");
		result = -EIO;
		goto fail;
	}		
#endif

	/* Initialize the hw data */
        hfa384x_create(hw, wlandev->netdev->irq, 0, mem);
	hw->wlandev = wlandev;

	/* Do a chip-level reset on the MAC */
	if (prism2_doreset) {
		result = hfa384x_corereset(hw, 
				prism2_reset_holdtime, 
				prism2_reset_settletime, 0);
		if (result != 0) {
			WLAN_LOG_ERROR(
				"%s: hfa384x_corereset() failed.\n", 
				dev_info);
			unregister_wlandev(wlandev);
			hfa384x_destroy(hw);
			result = -EIO;
			goto fail;
		}
	}

        pci_set_drvdata(pdev, wlandev);

	/* Shouldn't actually hook up the IRQ until we 
	 * _know_ things are alright.  A test routine would help.
	 */
       	request_irq(wlandev->netdev->irq, hfa384x_interrupt, 
		SA_SHIRQ, wlandev->name, wlandev);

	wlandev->msdstate = WLAN_MSD_HWPRESENT;

	result = 0;
	goto done;

 fail:
	pci_set_drvdata(pdev, NULL);
	if (wlandev)	kfree(wlandev);
	if (hw)		kfree(hw);
        if (mem)        iounmap((void *) mem);
	pci_release_regions(pdev);
        pci_disable_device(pdev);

 done:
	DBFEXIT;
	return result;
}

static int _pcc_get_status(u_short sock, u_int *value)
{
	u_int status;

	pr_debug("m32r_cfc: _pcc_get_status:\n");
	status = pcc_get(sock, (unsigned int)PLD_CFSTS);
	*value = (status) ? SS_DETECT : 0;
	pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status);

#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
	if ( status ) {
		/* enable CF power */
		status = inw((unsigned int)PLD_CPCR);
		if (!(status & PLD_CPCR_CF)) {
			pr_debug("m32r_cfc: _pcc_get_status: "
				 "power on (CPCR=0x%08x)\n", status);
			status |= PLD_CPCR_CF;
			outw(status, (unsigned int)PLD_CPCR);
			udelay(100);
		}
		*value |= SS_POWERON;

		pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
		udelay(100);

		*value |= SS_READY; 		/* always ready */
		*value |= SS_3VCARD;
	} else {
		/* disable CF power */
		status = inw((unsigned int)PLD_CPCR);
		status &= ~PLD_CPCR_CF;
		outw(status, (unsigned int)PLD_CPCR);
		udelay(100);
		pr_debug("m32r_cfc: _pcc_get_status: "
			 "power off (CPCR=0x%08x)\n", status);
	}
#elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
	if ( status ) {
		status = pcc_get(sock, (unsigned int)PLD_CPCR);
		if (status == 0) { /* power off */
			pcc_set(sock, (unsigned int)PLD_CPCR, 1);
			pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
			udelay(50);
		}
		*value |= SS_POWERON;

		pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
		udelay(50);
		pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
		udelay(25); /* for IDE reset */
		pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
		mdelay(2);  /* for IDE reset */

		*value |= SS_READY;
		*value |= SS_3VCARD;
	} else {
		/* disable CF power */
	        pcc_set(sock, (unsigned int)PLD_CPCR, 0);
		udelay(100);
		pr_debug("m32r_cfc: _pcc_get_status: "
			 "power off (CPCR=0x%08x)\n", status);
	}
#else
#error no platform configuration
#endif
	pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
		 sock, *value);
	return 0;
} /* _get_status */