/*
 * Determine device configuration for a machine.
 */
void
cpu_configure(void)
{

	intr_init();
	calc_delayconst();

	/* Make sure that timers run at CPU frequency */
	mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);

	if (config_rootfound("plb", &local_plb_devs) == NULL)
		panic("configure: plb not configured");

	printf("biomask %x netmask %x ttymask %x\n", (u_short)imask[IPL_BIO],
	    (u_short)imask[IPL_NET], (u_short)imask[IPL_TTY]);
	
	(void)spl0();

	/*
	 * Now allow hardware interrupts.
	 */
	asm volatile ("wrteei 1");
}

/*************************************************************************
 *  void l2cache_enable()
 *
 ************************************************************************/
static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
{
	mtdcr( L2_CACHE_CFG, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */

	mtdcr( L2_CACHE_ADDR, 0 );		/* set L2_ADDR with all zeros */

	mtdcr( L2_CACHE_CMD, 0x80000000 );	/* issue HCLEAR command via L2_CMD */

	while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */

	mtdcr( L2_CACHE_CMD, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */

	mtdcr( L2_CACHE_CMD, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */

	mtdcr( L2_CACHE_SNP0, 0 );		/* snoop registers */
	mtdcr( L2_CACHE_SNP1, 0 );

	__asm__ volatile ("sync");		/* msync */

	mtdcr( L2_CACHE_CFG, 0xe0000000 );	/* inst and data use L2 */

	__asm__ volatile ("sync");
}

int wait_for_dram_init_complete(void)
{
	u32 val;
	int wait = 0;

	/*
	 * Wait for 'DRAM initialization complete' bit in status register
	 */
	mtdcr(ddrcfga, DDR0_00);

	while (wait != 0xffff) {
		val = mfdcr(ddrcfgd);
		if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
			/* 'DRAM initialization complete' bit */
			return 0;
		else
			wait++;
	}

	debug("DRAM initialization complete bit in status register did not rise\n");

	return -1;
}

static int emulate_mfdcr(struct kvm_vcpu *vcpu, int rt, int dcrn)
{
	/* The guest may access CPR0 registers to determine the timebase
	 * frequency, and it must know the real host frequency because it
	 * can directly access the timebase registers.
	 *
	 * It would be possible to emulate those accesses in userspace,
	 * but userspace can really only figure out the end frequency.
	 * We could decompose that into the factors that compute it, but
	 * that's tricky math, and it's easier to just report the real
	 * CPR0 values.
	 */
	switch (dcrn) {
	case DCRN_CPR0_CONFIG_ADDR:
		kvmppc_set_gpr(vcpu, rt, vcpu->arch.cpr0_cfgaddr);
		break;
	case DCRN_CPR0_CONFIG_DATA:
		local_irq_disable();
		mtdcr(DCRN_CPR0_CONFIG_ADDR,
			  vcpu->arch.cpr0_cfgaddr);
		kvmppc_set_gpr(vcpu, rt,
			       mfdcr(DCRN_CPR0_CONFIG_DATA));
		local_irq_enable();
		break;
	default:
		vcpu->run->dcr.dcrn = dcrn;
		vcpu->run->dcr.data =  0;
		vcpu->run->dcr.is_write = 0;
		vcpu->arch.dcr_is_write = 0;
		vcpu->arch.io_gpr = rt;
		vcpu->arch.dcr_needed = 1;
		kvmppc_account_exit(vcpu, DCR_EXITS);
		return EMULATE_DO_DCR;
	}

	return EMULATE_DONE;
}

void __ft_board_setup(void *blob, bd_t *bd)
{
	int rc;
	int i;
	u32 bxcr;
	u32 ranges[EBC_NUM_BANKS * 4];
	u32 *p = ranges;
	char *ebc_path = "/plb/opb/ebc";

	ft_cpu_setup(blob, bd);

	/*
	 * Read 4xx EBC bus bridge registers to get mappings of the
	 * peripheral banks into the OPB/PLB address space
	 */
	for (i = 0; i < EBC_NUM_BANKS; i++) {
		mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
		bxcr = mfdcr(EBC0_CFGDATA);

		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
			*p++ = i;
			*p++ = 0;
			*p++ = bxcr & EBC_BXCR_BAS_MASK;
			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
		}
	}

	/* Some 405 PPC's have EBC as direct PLB child in the dts */
	if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
		strcpy(ebc_path, "/plb/ebc");
	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
				  (p - ranges) * sizeof(u32), 1);
	if (rc) {
		printf("Unable to update property EBC mappings, err=%s\n",
		       fdt_strerror(rc));
	}
}

/*-----------------------------------------------------------------------------+
 * wait_for_dlllock.
 +----------------------------------------------------------------------------*/
static int wait_for_dlllock(void)
{
	unsigned long val;
	int wait = 0;

	/* -----------------------------------------------------------+
	 * Wait for the DCC master delay line to finish calibration
	 * ----------------------------------------------------------*/
	mtdcr(ddrcfga, DDR0_17);
	val = DDR0_17_DLLLOCKREG_UNLOCKED;

	while (wait != 0xffff) {
		val = mfdcr(ddrcfgd);
		if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
			/* dlllockreg bit on */
			return 0;
		else
			wait++;
	}
	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
	debug("Waiting for dlllockreg bit to raise\n");

	return -1;
}

int board_early_init_f (void)
{
	uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr( ebccfga, xbcfg );
	reg = mfdcr( ebccfgd );
	mtdcr( ebccfgd, reg | 0x04000000 );	/* Set ATC */

	mtebc( pb0ap, 0x92015480 );	/* FLASH/SRAM */
	mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
	/* test-only: other regs still missing... */

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr( uic0sr, 0xffffffff );    /* clear all */
	mtdcr( uic0er, 0x00000000 );    /* disable all */
	mtdcr( uic0cr, 0x00000009 );    /* SMI & UIC1 crit are critical */
	mtdcr( uic0pr, 0xfffffe13 );    /* per ref-board manual */
	mtdcr( uic0tr, 0x01c00008 );    /* per ref-board manual */
	mtdcr( uic0vr, 0x00000001 );    /* int31 highest, base=0x000 */
	mtdcr( uic0sr, 0xffffffff );    /* clear all */

	mtdcr( uic1sr, 0xffffffff );    /* clear all */
	mtdcr( uic1er, 0x00000000 );    /* disable all */
	mtdcr( uic1cr, 0x00000000 );    /* all non-critical */
	mtdcr( uic1pr, 0xffffe0ff );    /* per ref-board manual */
	mtdcr( uic1tr, 0x00ffc000 );    /* per ref-board manual */
	mtdcr( uic1vr, 0x00000001 );    /* int31 highest, base=0x000 */
	mtdcr( uic1sr, 0xffffffff );    /* clear all */

	return 0;
}

int checkcpu (void)
{
#if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
	uint pvr = get_pvr();
	ulong clock = gd->cpu_clk;
	char buf[32];

#if !defined(CONFIG_IOP480)
	char addstr[64] = "";
	sys_info_t sys_info;

	puts ("CPU:   ");

	get_sys_info(&sys_info);

	puts("AMCC PowerPC 4");

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
    defined(CONFIG_405EX)
	puts("05");
#endif
#if defined(CONFIG_440)
	puts("40");
#endif

	switch (pvr) {
	case PVR_405GP_RB:
		puts("GP Rev. B");
		break;

	case PVR_405GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_405GP_RD:
		puts("GP Rev. D");
		break;

#ifdef CONFIG_405GP
	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
		puts("GP Rev. E");
		break;
#endif

	case PVR_405CR_RA:
		puts("CR Rev. A");
		break;

	case PVR_405CR_RB:
		puts("CR Rev. B");
		break;

#ifdef CONFIG_405CR
	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
		puts("CR Rev. C");
		break;
#endif

	case PVR_405GPR_RB:
		puts("GPr Rev. B");
		break;

	case PVR_405EP_RB:
		puts("EP Rev. B");
		break;

	case PVR_405EZ_RA:
		puts("EZ Rev. A");
		break;

	case PVR_405EX1_RA:
		puts("EX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EX2_RA:
		puts("EX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EXR1_RA:
		puts("EXr Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RA:
		puts("EXr Rev. A");
		strcpy(addstr, "No Security support");
		break;

#if defined(CONFIG_440)
	case PVR_440GP_RB:
		puts("GP Rev. B");
		/* See errata 1.12: CHIP_4 */
		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
				"Resetting chip ...\n");
			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
//.........这里部分代码省略.........

unsigned long flash_init (void)
{
	unsigned long size_b0, size_b1;
	int i;
	uint pbcr;
	unsigned long base_b0, base_b1;

	/* Init: no FLASHes known */
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
		flash_info[i].flash_id = FLASH_UNKNOWN;
	}

	/* Static FLASH Bank configuration here - FIXME XXX */

	base_b0 = FLASH_BASE0_PRELIM;
	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
				size_b0, size_b0 << 20);
	}

	base_b1 = FLASH_BASE1_PRELIM;
	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);

	/* Re-do sizing to get full correct info */

	if (size_b1) {
		if (size_b1 < (1 << 20)) {
			/* minimum CS size on PPC405GP is 1MB !!! */
			size_b1 = 1 << 20;
		}
		base_b1 = -size_b1;
		mtdcr (EBC0_CFGADDR, PB0CR);
		pbcr = mfdcr (EBC0_CFGDATA);
		mtdcr (EBC0_CFGADDR, PB0CR);
		pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
		mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
		printf("size_b1=%x base_b1=%x PB1CR = %x\n",
		       size_b1, base_b1, pbcr); /* test-only */
#endif
	}

	if (size_b0) {
		if (size_b0 < (1 << 20)) {
			/* minimum CS size on PPC405GP is 1MB !!! */
			size_b0 = 1 << 20;
		}
		base_b0 = base_b1 - size_b0;
		mtdcr (EBC0_CFGADDR, PB1CR);
		pbcr = mfdcr (EBC0_CFGDATA);
		mtdcr (EBC0_CFGADDR, PB1CR);
		pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
		mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
		printf("size_b0=%x base_b0=%x PB0CR = %x\n",
		       size_b0, base_b0, pbcr); /* test-only */
#endif
	}

	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

	flash_get_offsets (base_b0, &flash_info[0]);

	/* monitor protection ON by default */
	flash_protect (FLAG_PROTECT_SET,
			base_b0 + size_b0 - monitor_flash_len,
			base_b0 + size_b0 - 1, &flash_info[0]);

	if (size_b1) {
		/* Re-do sizing to get full correct info */
		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);

		flash_get_offsets (base_b1, &flash_info[1]);

		/* monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
				base_b1 + size_b1 - monitor_flash_len,
				base_b1 + size_b1 - 1, &flash_info[1]);
		/* monitor protection OFF by default (one is enough) */
		flash_protect (FLAG_PROTECT_CLEAR,
				base_b0 + size_b0 - monitor_flash_len,
				base_b0 + size_b0 - 1, &flash_info[0]);
	} else {
		flash_info[1].flash_id = FLASH_UNKNOWN;
		flash_info[1].sector_count = -1;
	}

	flash_info[0].size = size_b0;
	flash_info[1].size = size_b1;

	return (size_b0 + size_b1);
}

unsigned long flash_init (void)
{
	unsigned long size_b0, size_b1;
	int i;
	uint pbcr;
	unsigned long base_b0, base_b1;

	/* Init: no FLASHes known */
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
		flash_info[i].flash_id = FLASH_UNKNOWN;
	}

	/* Static FLASH Bank configuration here - FIXME XXX */

	base_b0 = FLASH_BASE0_PRELIM;
	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
			size_b0, size_b0 << 20);
	}

	base_b1 = FLASH_BASE1_PRELIM;
	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);

	/* Re-do sizing to get full correct info */

	if (size_b1) {
		mtdcr (ebccfga, pb0cr);
		pbcr = mfdcr (ebccfgd);
		mtdcr (ebccfga, pb0cr);
		base_b1 = -size_b1;
		pbcr = (pbcr & 0x0001ffff) | base_b1 |
				(((size_b1 / 1024 / 1024) - 1) << 17);
		mtdcr (ebccfgd, pbcr);
		/*          printf("pb1cr = %x\n", pbcr); */
	}

	if (size_b0) {
		mtdcr (ebccfga, pb1cr);
		pbcr = mfdcr (ebccfgd);
		mtdcr (ebccfga, pb1cr);
		base_b0 = base_b1 - size_b0;
		pbcr = (pbcr & 0x0001ffff) | base_b0 |
				(((size_b0 / 1024 / 1024) - 1) << 17);
		mtdcr (ebccfgd, pbcr);
		/*            printf("pb0cr = %x\n", pbcr); */
	}

	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

	flash_get_offsets (base_b0, &flash_info[0]);

	/* monitor protection ON by default */
	flash_protect (FLAG_PROTECT_SET,
			base_b0 + size_b0 - monitor_flash_len,
			base_b0 + size_b0 - 1, &flash_info[0]);

	if (size_b1) {
		/* Re-do sizing to get full correct info */
		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);

		flash_get_offsets (base_b1, &flash_info[1]);

		/* monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
				base_b1 + size_b1 - monitor_flash_len,
				base_b1 + size_b1 - 1, &flash_info[1]);
		/* monitor protection OFF by default (one is enough) */
		flash_protect (FLAG_PROTECT_CLEAR,
				base_b0 + size_b0 - monitor_flash_len,
				base_b0 + size_b0 - 1, &flash_info[0]);
	} else {
		flash_info[1].flash_id = FLASH_UNKNOWN;
		flash_info[1].sector_count = -1;
	}

	flash_info[0].size = size_b0;
	flash_info[1].size = size_b1;

	return (size_b0 + size_b1);
}

void
ppc4xx_enable_dma(unsigned int dmanr)
{
	unsigned int control;
	ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
	unsigned int status_bits[] = { DMA_CS0 | DMA_TS0 | DMA_CH0_ERR,
				       DMA_CS1 | DMA_TS1 | DMA_CH1_ERR,
				       DMA_CS2 | DMA_TS2 | DMA_CH2_ERR,
				       DMA_CS3 | DMA_TS3 | DMA_CH3_ERR};

	if (p_dma_ch->in_use) {
		printk("enable_dma: channel %d in use\n", dmanr);
		return;
	}

	if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
		printk("enable_dma: bad channel: %d\n", dmanr);
		return;
	}

	if (p_dma_ch->mode == DMA_MODE_READ) {
		/* peripheral to memory */
		ppc4xx_set_src_addr(dmanr, 0);
		ppc4xx_set_dst_addr(dmanr, p_dma_ch->addr);
	} else if (p_dma_ch->mode == DMA_MODE_WRITE) {
		/* memory to peripheral */
		ppc4xx_set_src_addr(dmanr, p_dma_ch->addr);
		ppc4xx_set_dst_addr(dmanr, 0);
	}

	/* for other xfer modes, the addresses are already set */
	control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));

	control &= ~(DMA_TM_MASK | DMA_TD);	/* clear all mode bits */
	if (p_dma_ch->mode == DMA_MODE_MM) {
		/* software initiated memory to memory */
		control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
	}

	mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);

	/*
	 * Clear the CS, TS, RI bits for the channel from DMASR.  This
	 * has been observed to happen correctly only after the mode and
	 * ETD/DCE bits in DMACRx are set above.  Must do this before
	 * enabling the channel.
	 */

	mtdcr(DCRN_DMASR, status_bits[dmanr]);

	/*
	 * For device-paced transfers, Terminal Count Enable apparently
	 * must be on, and this must be turned on after the mode, etc.
	 * bits are cleared above (at least on Redwood-6).
	 */

	if ((p_dma_ch->mode == DMA_MODE_MM_DEVATDST) ||
	    (p_dma_ch->mode == DMA_MODE_MM_DEVATSRC))
		control |= DMA_TCE_ENABLE;

	/*
	 * Now enable the channel.
	 */

	control |= (p_dma_ch->mode | DMA_CE_ENABLE);

	mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);

	p_dma_ch->in_use = 1;
}

struct bi_record *
decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
{
#ifdef INTERACTIVE_CONSOLE
    int timer = 0;
    char ch;
#endif
    char *cp;
    struct bi_record *rec;
    unsigned long initrd_loc = 0, TotalMemory = 0;

#if defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
    com_port = serial_init(0, NULL);
#endif

#if defined(PPC4xx_EMAC0_MR0)
    /* Reset MAL */
    mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);
    /* Wait for reset */
    while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {};
    /* Reset EMAC */
    *(volatile unsigned long *)PPC4xx_EMAC0_MR0 = 0x20000000;
    __asm__ __volatile__("eieio");
#endif

    /*
     * Call get_mem_size(), which is memory controller dependent,
     * and we must have the correct file linked in here.
     */
    TotalMemory = get_mem_size();

    /* assume the chunk below 8M is free */
    end_avail = (char *)0x00800000;

    /*
     * Reveal where we were loaded at and where we
     * were relocated to.
     */
    puts("loaded at:     "); puthex(load_addr);
    puts(" "); puthex((unsigned long)(load_addr + (4*num_words)));
    puts("\n");
    if ( (unsigned long)load_addr != (unsigned long)&start )
    {
        puts("relocated to:  "); puthex((unsigned long)&start);
        puts(" ");
        puthex((unsigned long)((unsigned long)&start + (4*num_words)));
        puts("\n");
    }

    /*
     * We link ourself to 0x00800000.  When we run, we relocate
     * ourselves there.  So we just need __image_begin for the
     * start. -- Tom
     */
    zimage_start = (char *)(unsigned long)(&__image_begin);
    zimage_size = (unsigned long)(&__image_end) -
            (unsigned long)(&__image_begin);

    initrd_size = (unsigned long)(&__ramdisk_end) -
        (unsigned long)(&__ramdisk_begin);

    /*
     * The zImage and initrd will be between start and _end, so they've
     * already been moved once.  We're good to go now. -- Tom
     */
    avail_ram = (char *)PAGE_ALIGN((unsigned long)_end);
    puts("zimage at:     "); puthex((unsigned long)zimage_start);
    puts(" "); puthex((unsigned long)(zimage_size+zimage_start));
    puts("\n");

    if ( initrd_size ) {
        puts("initrd at:     ");
        puthex((unsigned long)(&__ramdisk_begin));
        puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
    }

#ifndef CONFIG_40x /* don't overwrite the 40x image located at 0x00400000! */
    avail_ram = (char *)0x00400000;
#endif
    end_avail = (char *)0x00800000;
    puts("avail ram:     "); puthex((unsigned long)avail_ram); puts(" ");
    puthex((unsigned long)end_avail); puts("\n");

    if (keyb_present)
        CRT_tstc();  /* Forces keyboard to be initialized */

    /* Display standard Linux/PPC boot prompt for kernel args */
    puts("\nLinux/PPC load: ");
    cp = cmd_line;
    memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
    while ( *cp ) putc(*cp++);

#ifdef INTERACTIVE_CONSOLE
    /*
     * If they have a console, allow them to edit the command line.
     * Otherwise, don't bother wasting the five seconds.
     */
    while (timer++ < 5*1000) {
        if (tstc()) {
            while ((ch = getc()) != '\n' && ch != '\r') {
//.........这里部分代码省略.........

/*
 *   Create a scatter/gather list handle.  This is simply a structure which
 *   describes a scatter/gather list.
 *
 *   A handle is returned in "handle" which the driver should save in order to 
 *   be able to access this list later.  A chunk of memory will be allocated 
 *   to be used by the API for internal management purposes, including managing 
 *   the sg list and allocating memory for the sgl descriptors.  One page should 
 *   be more than enough for that purpose.  Perhaps it's a bit wasteful to use 
 *   a whole page for a single sg list, but most likely there will be only one 
 *   sg list per channel.
 *
 *   Interrupt notes:
 *   Each sgl descriptor has a copy of the DMA control word which the DMA engine
 *   loads in the control register.  The control word has a "global" interrupt 
 *   enable bit for that channel. Interrupts are further qualified by a few bits
 *   in the sgl descriptor count register.  In order to setup an sgl, we have to
 *   know ahead of time whether or not interrupts will be enabled at the completion
 *   of the transfers.  Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST
 *   be called before calling alloc_dma_handle().  If the interrupt mode will never
 *   change after powerup, then enable_dma_interrupt()/disable_dma_interrupt() 
 *   do not have to be called -- interrupts will be enabled or disabled based
 *   on how the channel was configured after powerup by the hw_init_dma_channel()
 *   function.  Each sgl descriptor will be setup to interrupt if an error occurs;
 *   however, only the last descriptor will be setup to interrupt. Thus, an 
 *   interrupt will occur (if interrupts are enabled) only after the complete
 *   sgl transfer is done.
 */
int
ppc4xx_alloc_dma_handle(sgl_handle_t * phandle, unsigned int mode, unsigned int dmanr)
{
	sgl_list_info_t *psgl;
	dma_addr_t dma_addr;
	ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
	uint32_t sg_command;
	void *ret;

	if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
		printk("ppc4xx_alloc_dma_handle: invalid channel 0x%x\n", dmanr);
		return DMA_STATUS_BAD_CHANNEL;
	}

	if (!phandle) {
		printk("ppc4xx_alloc_dma_handle: null handle pointer\n");
		return DMA_STATUS_NULL_POINTER;
	}

	/* Get a page of memory, which is zeroed out by consistent_alloc() */
	ret = consistent_alloc(GFP_KERNEL, DMA_PPC4xx_SIZE, &dma_addr);
	if (ret != NULL) {
		memset(ret, 0, DMA_PPC4xx_SIZE);
		psgl = (sgl_list_info_t *) ret;
	}

	if (psgl == NULL) {
		*phandle = (sgl_handle_t) NULL;
		return DMA_STATUS_OUT_OF_MEMORY;
	}

	psgl->dma_addr = dma_addr;
	psgl->dmanr = dmanr;

	/*
	 * Modify and save the control word. These words will be
	 * written to each sgl descriptor.  The DMA engine then
	 * loads this control word into the control register
	 * every time it reads a new descriptor.
	 */
	psgl->control = p_dma_ch->control;
	/* Clear all mode bits */
	psgl->control &= ~(DMA_TM_MASK | DMA_TD);
	/* Save control word and mode */
	psgl->control |= (mode | DMA_CE_ENABLE);

	/* In MM mode, we must set ETD/TCE */
	if (mode == DMA_MODE_MM)
		psgl->control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;

	if (p_dma_ch->int_enable) {
		/* Enable channel interrupt */
		psgl->control |= DMA_CIE_ENABLE;
	} else {
		psgl->control &= ~DMA_CIE_ENABLE;
	}

	sg_command = mfdcr(DCRN_ASGC);
	switch (dmanr) {
	case 0:
		sg_command |= SSG0_MASK_ENABLE;
		break;
	case 1:
		sg_command |= SSG1_MASK_ENABLE;
		break;
	case 2:
		sg_command |= SSG2_MASK_ENABLE;
		break;
	case 3:
		sg_command |= SSG3_MASK_ENABLE;
		break;
	default:
//.........这里部分代码省略.........

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	bd_t *bd = gd->bd;
	char *	tmp;                    /* Temporary char pointer      */
	unsigned long cntrl0Reg;

#ifdef CONFIG_CPCI405_VER2
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;

	/*
	 * On CPCI-405 version 2 the environment is saved in eeprom!
	 * FPGA can be gzip compressed (malloc) and booted this late.
	 */

	if (cpci405_version() >= 2) {
		/*
		 * Setup GPIO pins (CS6+CS7 as GPIO)
		 */
		cntrl0Reg = mfdcr(cntrl0);
		mtdcr(cntrl0, cntrl0Reg | 0x00300000);

		dst = malloc(CFG_FPGA_MAX_SIZE);
		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
			printf ("GUNZIP ERROR - must RESET board to recover\n");
			do_reset (NULL, 0, 0, NULL);
		}

		status = fpga_boot(dst, len);
		if (status != 0) {
			printf("\nFPGA: Booting failed ");
			switch (status) {
			case ERROR_FPGA_PRG_INIT_LOW:
				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_INIT_HIGH:
				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_DONE:
				printf("(Timeout: DONE not high after programming FPGA)\n ");
				break;
			}

			/* display infos on fpgaimage */
			index = 15;
			for (i=0; i<4; i++) {
				len = dst[index];
				printf("FPGA: %s\n", &(dst[index+1]));
				index += len+3;
			}
			putc ('\n');
			/* delayed reboot */
			for (i=20; i>0; i--) {
				printf("Rebooting in %2d seconds \r",i);
				for (index=0;index<1000;index++)
					udelay(1000);
			}
			putc ('\n');
			do_reset(NULL, 0, 0, NULL);
		}

		/* restore gpio/cs settings */
		mtdcr(cntrl0, cntrl0Reg);

		puts("FPGA:  ");

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("%s ", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');

		free(dst);

		/*
		 * Reset FPGA via FPGA_DATA pin
		 */
		SET_FPGA(FPGA_PRG | FPGA_CLK);
		udelay(1000); /* wait 1ms */
		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
		udelay(1000); /* wait 1ms */

		if (cpci405_version() == 3) {
			volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
			volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;

			/*
			 * Enable outputs in fpga on version 3 board
			 */
			*fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;

			/*
//.........这里部分代码省略.........

//.........这里部分代码省略.........
		      CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
		      &flash_info[cfi_flash_num_flash_banks - 1]);

	/*
	 * USB suff...
	 */

	/* Reset USB */
	/* Reset of USB2PHY0 must be active at least 10 us  */
	mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
	udelay(2000);

	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
	      SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
	      SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
	udelay(2000);

	/* Errata CHIP_6 */

	/* 1. Set internal PHY configuration */
	/* SDR Setting */
	mfsdr(SDR0_PFC1, sdr0_pfc1);
	mfsdr(SDR0_USB0, usb2d0cr);
	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	mfsdr(SDR0_USB2H0CR, usb2h0cr);

	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/

	/*
	 * An 8-bit/60MHz interface is the only possible alternative
	 * when connecting the Device to the PHY
	 */
	usb2h0cr   = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
	usb2h0cr   = usb2h0cr |  SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/

	mtsdr(SDR0_PFC1, sdr0_pfc1);
	mtsdr(SDR0_USB0, usb2d0cr);
	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	mtsdr(SDR0_USB2H0CR, usb2h0cr);

	/* 2. De-assert internal PHY reset */
	mfsdr(SDR0_SRST1, sdr0_srst);
	sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
	mtsdr(SDR0_SRST1, sdr0_srst);

	/* 3. Wait for more than 1 ms */
	udelay(2000);

	/* 4. De-assert USB 2.0 Host main reset */
	mfsdr(SDR0_SRST0, sdr0_srst);
	sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
	mtsdr(SDR0_SRST0, sdr0_srst);
	udelay(1000);

	/* 5. De-assert reset of OPB2 cores */
	mfsdr(SDR0_SRST1, sdr0_srst);
	sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
	mtsdr(SDR0_SRST1, sdr0_srst);
	udelay(1000);

	/* 6. Set EHCI Configure FLAG */

	/* 7. Reassert internal PHY reset: */
	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
	udelay(1000);

	/*
	 * Clear resets
	 */
	mtsdr(SDR0_SRST1, 0x00000000);
	mtsdr(SDR0_SRST0, 0x00000000);

	printf("USB:   Host(int phy) Device(ext phy)\n");

	/*
	 * Clear PLB4A0_ACR[WRP]
	 * This fix will make the MAL burst disabling patch for the Linux
	 * EMAC driver obsolete.
	 */
	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
	mtdcr(PLB4A0_ACR, reg);

	/*
	 * Init matrix keyboard
	 */
	misc_init_r_kbd();

	return 0;
}

/*-----------------------------------------------------------------------------+
 * denali_core_search_data_eye.
 +----------------------------------------------------------------------------*/
void denali_core_search_data_eye(unsigned long memory_size)
{
	int k, j;
	u32 val;
	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
	volatile u32 *ram_pointer;
	u32 test[NUM_TRIES] = {
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };

	ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);

	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
		/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/

		/* -----------------------------------------------------------+
		 * De-assert 'start' parameter.
		 * ----------------------------------------------------------*/
		mtdcr(ddrcfga, DDR0_02);
		val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
		mtdcr(ddrcfgd, val);

		/* -----------------------------------------------------------+
		 * Set 'wr_dqs_shift'
		 * ----------------------------------------------------------*/
		mtdcr(ddrcfga, DDR0_09);
		val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
			| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
		mtdcr(ddrcfgd, val);

		/* -----------------------------------------------------------+
		 * Set 'dqs_out_shift' = wr_dqs_shift + 32
		 * ----------------------------------------------------------*/
		dqs_out_shift = wr_dqs_shift + 32;
		mtdcr(ddrcfga, DDR0_22);
		val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
			| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
		mtdcr(ddrcfgd, val);

		passing_cases = 0;

		for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
			/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
			/* -----------------------------------------------------------+
			 * Set 'dll_dqs_delay_X'.
			 * ----------------------------------------------------------*/
			/* dll_dqs_delay_0 */
			mtdcr(ddrcfga, DDR0_17);
			val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
				| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
			mtdcr(ddrcfgd, val);
			/* dll_dqs_delay_1 to dll_dqs_delay_4 */
			mtdcr(ddrcfga, DDR0_18);
			val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
				| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
				| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
				| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
				| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
			mtdcr(ddrcfgd, val);
			/* dll_dqs_delay_5 to dll_dqs_delay_8 */
			mtdcr(ddrcfga, DDR0_19);
			val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
				| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
				| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
				| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
				| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
			mtdcr(ddrcfgd, val);

			ppcMsync();
			ppcMbar();

			/* -----------------------------------------------------------+
			 * Assert 'start' parameter.
			 * ----------------------------------------------------------*/
			mtdcr(ddrcfga, DDR0_02);
			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
			mtdcr(ddrcfgd, val);

			ppcMsync();
			ppcMbar();
//.........这里部分代码省略.........

unsigned long flash_init (void)
{
	unsigned long size_b0, size_b1;
	int i;
	uint pbcr;
	unsigned long base_b0, base_b1;

	/* Init: no FLASHes known */
	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
		flash_info[i].flash_id = FLASH_UNKNOWN;
	}

	/* Static FLASH Bank configuration here - FIXME XXX */

	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[0]);

	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
			size_b0, size_b0<<20);
	}

	/* Only one bank */
	if (CFG_MAX_FLASH_BANKS == 1) {
		/* Setup offsets */
		flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);

		/* Monitor protection ON by default */
#if 0	/* sand: */
		(void)flash_protect(FLAG_PROTECT_SET,
			FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
			FLASH_BASE1_PRELIM-1+size_b0,
			&flash_info[0]);
#else
		(void)flash_protect(FLAG_PROTECT_SET,
			CFG_MONITOR_BASE,
			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
			&flash_info[0]);
#endif
		size_b1 = 0 ;
		flash_info[0].size = size_b0;
	} else {	/* 2 banks */
		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);

		/* Re-do sizing to get full correct info */
		if (size_b1) {
			mtdcr(ebccfga, pb0cr);
			pbcr = mfdcr(ebccfgd);
			mtdcr(ebccfga, pb0cr);
			base_b1 = -size_b1;
			pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
			mtdcr(ebccfgd, pbcr);
		}

		if (size_b0) {
			mtdcr(ebccfga, pb1cr);
			pbcr = mfdcr(ebccfgd);
			mtdcr(ebccfga, pb1cr);
			base_b0 = base_b1 - size_b0;
			pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
			mtdcr(ebccfgd, pbcr);
		}

		size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);

		flash_get_offsets (base_b0, &flash_info[0]);

		/* monitor protection ON by default */
#if 0	/* sand: */
		(void)flash_protect(FLAG_PROTECT_SET,
			FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
			FLASH_BASE1_PRELIM-1+size_b0,
			&flash_info[0]);
#else
		(void)flash_protect(FLAG_PROTECT_SET,
			CFG_MONITOR_BASE,
			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
			&flash_info[0]);
#endif

		if (size_b1) {
			/* Re-do sizing to get full correct info */
			size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);

			flash_get_offsets (base_b1, &flash_info[1]);

			/* monitor protection ON by default */
			(void)flash_protect(FLAG_PROTECT_SET,
				base_b1+size_b1-CFG_MONITOR_LEN,
				base_b1+size_b1-1,
				&flash_info[1]);
			/* monitor protection OFF by default (one is enough) */
			(void)flash_protect(FLAG_PROTECT_CLEAR,
				base_b0+size_b0-CFG_MONITOR_LEN,
				base_b0+size_b0-1,
				&flash_info[0]);
		} else {
			flash_info[1].flash_id = FLASH_UNKNOWN;
			flash_info[1].sector_count = -1;
		}

//.........这里部分代码省略.........

int misc_init_r(void)
{
	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
	u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
	u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
	u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	unsigned long CPC0_CR0Reg;
	char *str;
	uchar *logo_addr;
	ulong logo_size;
	ushort minb, maxb;
	int result;

	/*
	 * Setup GPIO pins (CS6+CS7 as GPIO)
	 */
	CPC0_CR0Reg = mfdcr(CPC0_CR0);
	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);

	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf("GUNZIP ERROR - must RESET board to recover\n");
		do_reset(NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: "
			       "INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: "
			       "INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: "
			       "DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i = 0; i < 4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len + 3;
		}
		putc('\n');
		/* delayed reboot */
		for (i = 20; i > 0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index = 0; index < 1000; index++)
				udelay(1000);
		}
		putc('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	/* restore gpio/cs settings */
	mtdcr(CPC0_CR0, CPC0_CR0Reg);

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i = 0; i < 4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index + 1]));
		index += len + 3;
	}
	putc('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

	/*
	 * Write board revision in FPGA
	 */
	out_be16(fpga_ctrl2,
		 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));

	/*
	 * Enable power on PS/2 interface (with reset)
	 */
	out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
//.........这里部分代码省略.........

int board_early_init_f(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller