static void sr_clk_disable(struct omap_sr *sr)
{
	if (cpu_is_omap3630())
		sr_modify_reg(sr, ERRCONFIG_36XX, SR_IDLEMODE_MASK,
		SR_FORCE_IDLE);
	else
	/* set fclk, iclk- idle */
	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
		      SR_CLKACTIVITY_IOFF_FOFF);

	clk_disable(sr->clk);
	sr->is_sr_reset = 1;
}

static inline void omap_init_mbox(void)
{
	if (cpu_is_omap2420()) {
		mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources);
		mbox_device.resource = omap2_mbox_resources;
	} else if (cpu_is_omap3430() || cpu_is_omap3630()) {
		mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources);
		mbox_device.resource = omap3_mbox_resources;
	} else {
		return;
	}
	platform_device_register(&mbox_device);
}

static void __init omap3_evm_init_irq(void)
{
	omap_board_config = omap3_evm_config;
	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
	omap2_init_common_infrastructure();
	if (cpu_is_omap3630())
		omap2_init_common_devices(h8kds0un0mer4em_sdrc_params, NULL);
	else
		omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);

	omap_init_irq();
	gpmc_init();
}

static void __init omap_boxer_init(void)
{
	/*we need to have this enable function here to light up the BL*/
	boxer_panel_enable_lcd(&boxer_lcd_device);
	omap_i2c_init();
	/* Fix to prevent VIO leakage on wl127x */
//	wl127x_vio_leakage_fix();

	platform_add_devices(boxer_devices, ARRAY_SIZE(boxer_devices));

	omap_board_config = boxer_config;
	omap_board_config_size = ARRAY_SIZE(boxer_config);

	spi_register_board_info(boxer_spi_board_info,
				ARRAY_SIZE(boxer_spi_board_info));
#ifdef  CONFIG_TOUCHSCREEN_PIXCIR_I2C
	pixcir_dev_init();
#endif
#ifdef CONFIG_TOUCHSCREEN_CYTTSP_I2C
//    cyttsp_dev_init();
#endif

#ifdef CONFIG_INPUT_KXTF9
	kxtf9_dev_init();
#endif /* CONFIG_INPUT_KXTF9 */

#ifdef CONFIG_BATTERY_MAX17042
	max17042_dev_init();
#endif

#if defined(CONFIG_SND_SOC_DAC3100) || defined(CONFIG_SND_SOC_DAC3100_MODULE) || defined(CONFIG_SND_OMAP_SOC_OMAP3_EDP)
        audio_dac_3100_dev_init();
#endif
//	synaptics_dev_init();
//	msecure_init();
//	ldp_flash_init();
	omap_serial_init();
	usb_musb_init();
	boxer_backlight_init();
#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_ANDROID_MODULE)
	platform_device_register(&usb_mass_storage_device);
	// Set the device serial number passed in from the bootloader.
	if (system_serial_high != 0 || system_serial_low != 0) {
		snprintf(adb_serial_number, sizeof(adb_serial_number), "%08x%08x", system_serial_high, system_serial_low);
		adb_serial_number[16] = '\0';
		android_usb_pdata.serial_number = adb_serial_number;
	}
	platform_device_register(&android_usb_device);
#endif
        BUG_ON(!cpu_is_omap3630());
}

static int beagle_twl_gpio_setup(struct device *dev,
		unsigned gpio, unsigned ngpio)
{
	int r;

	mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
	mmc[0].gpio_cd = gpio + 0;
	omap_hsmmc_late_init(mmc);

	/*
	 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
	 * high / others active low)
	 * DVI reset GPIO is different between beagle revisions
	 */
	/* Valid for all -xM revisions */
	if (cpu_is_omap3630()) {
		/*
		 * gpio + 1 on Xm controls the TFP410's enable line (active low)
		 * gpio + 2 control varies depending on the board rev as below:
		 * P7/P8 revisions(prototype): Camera EN
		 * A2+ revisions (production): LDO (DVI, serial, led blocks)
		 */
		r = gpio_request_one(gpio + 1, GPIOF_OUT_INIT_LOW,
				     "nDVI_PWR_EN");
		if (r)
			pr_err("%s: unable to configure nDVI_PWR_EN\n",
				__func__);
		r = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH,
				     "DVI_LDO_EN");
		if (r)
			pr_err("%s: unable to configure DVI_LDO_EN\n",
				__func__);
	} else {
		/*
		 * REVISIT: need ehci-omap hooks for external VBUS
		 * power switch and overcurrent detect
		 */
		if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
			pr_err("%s: unable to configure EHCI_nOC\n", __func__);
	}
	dvi_panel.power_down_gpio = beagle_config.reset_gpio;

	gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
			"nEN_USB_PWR");

	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;

	return 0;
}

static void __init omap3_evm_init(void)
{
	omap3_evm_get_revision();

	if (cpu_is_omap3630())
		omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
	else
		omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);

	omap_board_config = omap3_evm_config;
	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);

	omap3_evm_i2c_init();

	omap_display_init(&omap3_evm_dss_data);

	omap_serial_init();
	omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);

	/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
	usb_nop_xceiv_register(0);

	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
		/* enable EHCI VBUS using GPIO22 */
		omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
		/* Select EHCI port on main board */
		omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
				   OMAP_PIN_INPUT_PULLUP);
		gpio_request_array(omap3_evm_ehci_gpios,
				   ARRAY_SIZE(omap3_evm_ehci_gpios));

		/* setup EHCI phy reset config */
		omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
		usbhs_bdata.reset_gpio_port[1] = 21;

		/* EVM REV >= E can supply 500mA with EXTVBUS programming */
		musb_board_data.power = 500;
		musb_board_data.extvbus = 1;
	} else {
		/* setup EHCI phy reset on MDC */
		omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
		usbhs_bdata.reset_gpio_port[1] = 135;
	}
	usb_musb_init(&musb_board_data);
	usbhs_init(&usbhs_bdata);
	omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
	omap3evm_init_smsc911x();
	omap3_evm_display_init();
	omap3_evm_wl12xx_init();
}

/* calculate clock rates using dividers in cinfo */
int dss_calc_clock_rates(struct dss_clock_info *cinfo)
{
	unsigned long prate;

	if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
						cinfo->fck_div == 0)
		return -EINVAL;

	prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));

	cinfo->fck = prate / cinfo->fck_div;

	return 0;
}

/*
 * Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
 * mode for MMC1 in case bootloader did not configure things.
 * Note that if the pins are used for MMC1, pbias-regulator
 * manages the IO voltage.
 */
static void __init omap3_gpio126_127_129(void)
{
	u32 reg;

	reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
	reg &= ~OMAP343X_PBIASLITEVMODE1;
	reg |= OMAP343X_PBIASLITEPWRDNZ1;
	omap_ctrl_writel(reg, OMAP343X_CONTROL_PBIAS_LITE);
	if (cpu_is_omap3630()) {
		reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
		reg |= OMAP36XX_GPIO_IO_PWRDNZ;
		omap_ctrl_writel(reg, OMAP34XX_CONTROL_WKUP_CTRL);
	}
}

static inline u16 get_vdd1_opp(void)
{
	int vdd1_opp;
	if (cpu_is_omap3630())
		/*
		 * if vdd1 opp table has any two opp's same freq than
		 * check the dsp opp instead
		 */
		vdd1_opp = get_dsp_opp();
	else
		vdd1_opp = get_opp(mpu_opps + MAX_VDD1_OPP, dpll1_ck->rate);

	return vdd1_opp;
}

/*
 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 * @clk: struct clk * of DPLL to set
 * @m: DPLL multiplier to set
 * @n: DPLL divider to set
 * @freqsel: FREQSEL value to set
 *
 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 * lock..  Returns -EINVAL upon error, or 0 upon success.
 */
static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
				      u16 freqsel)
{
	struct dpll_data *dd = clk->dpll_data;
	u8 dco, sd_div;
	u32 v;

	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
	_omap3_noncore_dpll_bypass(clk);

	/*
	 * Set jitter correction. No jitter correction for OMAP4 and 3630
	 * since freqsel field is no longer present
	 */
	if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
		v = __raw_readl(dd->control_reg);
		v &= ~dd->freqsel_mask;
		v |= freqsel << __ffs(dd->freqsel_mask);
		__raw_writel(v, dd->control_reg);
	}

	/* Set DPLL multiplier, divider */
	v = __raw_readl(dd->mult_div1_reg);
	v &= ~(dd->mult_mask | dd->div1_mask);
	v |= m << __ffs(dd->mult_mask);
	v |= (n - 1) << __ffs(dd->div1_mask);

	/* Configure dco and sd_div for dplls that have these fields */
	if (dd->dco_mask) {
		_lookup_dco(clk, &dco, m, n);
		v &= ~(dd->dco_mask);
		v |= dco << __ffs(dd->dco_mask);
	}
	if (dd->sddiv_mask) {
		_lookup_sddiv(clk, &sd_div, m, n);
		v &= ~(dd->sddiv_mask);
		v |= sd_div << __ffs(dd->sddiv_mask);
	}

	__raw_writel(v, dd->mult_div1_reg);

	/* We let the clock framework set the other output dividers later */

	/* REVISIT: Set ramp-up delay? */

	_omap3_noncore_dpll_lock(clk);

	return 0;
}

void dss_get_clock_div(struct dss_clock_info *cinfo)
{
	cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);

	if (cpu_is_omap34xx()) {
		unsigned long prate;
		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
		if (cpu_is_omap3630())
			cinfo->fck_div = prate / (cinfo->fck);
		else
			cinfo->fck_div = prate / (cinfo->fck / 2);
	} else {
		cinfo->fck_div = 0;
	}
}

static int __init omap_i2c_init(void)
{
	
         /* Disable OMAP 3630 internal pull-ups for I2Ci */
    if (cpu_is_omap3630()) {

        u32 prog_io;

        prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
        /* Program (bit 19)=1 to disable internal pull-up on I2C1 */
        prog_io |= OMAP3630_PRG_I2C1_PULLUPRESX;
        /* Program (bit 0)=1 to disable internal pull-up on I2C2 */
        prog_io |= OMAP3630_PRG_I2C2_PULLUPRESX;
        omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);

        prog_io = omap_ctrl_readl(OMAP36XX_CONTROL_PROG_IO2);
        /* Program (bit 7)=1 to disable internal pull-up on I2C3 */

#if (CONFIG_SAMSUNG_REL_HW_REV == 5)
	if(get_hw_revision() == 0x06) {
		printk("aalto_05_i2c setting\n");
	        prog_io &= ~OMAP3630_PRG_I2C3_PULLUPRESX;
	} else {
        	prog_io |= OMAP3630_PRG_I2C3_PULLUPRESX;
	}
#else
	prog_io |= OMAP3630_PRG_I2C3_PULLUPRESX;
#endif

        omap_ctrl_writel(prog_io, OMAP36XX_CONTROL_PROG_IO2);

        prog_io = omap_ctrl_readl(OMAP36XX_CONTROL_PROG_IO_WKUP1);
        /* Program (bit 5)=1 to disable internal pull-up on I2C4(SR) */
        prog_io |= OMAP3630_PRG_SR_PULLUPRESX;
        omap_ctrl_writel(prog_io, OMAP36XX_CONTROL_PROG_IO_WKUP1);
    }

    omap_register_i2c_bus(2, 400, NULL, board_i2c_boardinfo1,
			     ARRAY_SIZE(board_i2c_boardinfo1));
    
    omap_register_i2c_bus(1, 400, NULL, omap_board_i2c_boardinfo,
                         ARRAY_SIZE(omap_board_i2c_boardinfo));
   
    omap_register_i2c_bus(3, 400, NULL, board_i2c_boardinfo3,
				ARRAY_SIZE(board_i2c_boardinfo3));

    return 0;
}

int __init omap_twl_init(void)
{
	struct omap_pmic_description *desc = NULL;

	/* Reuse OMAP3430 values */
	if (cpu_is_omap3630()) {
		omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
		omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
		omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
		omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
	}
	if (cpu_is_omap44xx())
		desc = &twl6030_pmic_desc;

	return omap_pmic_register_data(omap_twl_map, desc);
}

/**
 * omap3_opp_init() - initialize omap3 opp table
 */
int __init omap3_opp_init(void)
{
	int r = -ENODEV;

	if (!cpu_is_omap34xx())
		return r;

	if (cpu_is_omap3630())
		r = omap_init_opp_table(omap36xx_opp_def_list,
			ARRAY_SIZE(omap36xx_opp_def_list));
	else
		r = omap_init_opp_table(omap34xx_opp_def_list,
			ARRAY_SIZE(omap34xx_opp_def_list));

	return r;
}

static void __init overo_opp_init(void)
{
	int r = 0;

	/* Initialize the omap3 opp table */
	if (omap3_opp_init()) {
		pr_err("%s: opp default init failed\n", __func__);
		return;
	}

	/* Custom OPP enabled for 36/3730 */
	if (cpu_is_omap3630()) {
		struct device *mpu_dev, *iva_dev;

		mpu_dev = omap_device_get_by_hwmod_name("mpu");

		if (omap3_has_iva())
			iva_dev = omap_device_get_by_hwmod_name("iva");

		if (!mpu_dev) {
			pr_err("%s: Aiee.. no mpu device? %p\n",
				__func__, mpu_dev);
			return;
		}
		/* Enable MPU 1GHz and lower opps */
		r = opp_enable(mpu_dev, 800000000);
		r |= opp_enable(mpu_dev, 1000000000);

		if (omap3_has_iva()) {
			/* Enable IVA 800MHz and lower opps */
			r |= opp_enable(iva_dev, 660000000);
			r |= opp_enable(iva_dev, 800000000);
		}

		if (r) {
			pr_err("%s: failed to enable higher opp %d\n",
				__func__, r);
			opp_disable(mpu_dev, 800000000);
			opp_disable(mpu_dev, 1000000000);
			if (omap3_has_iva()) {
				opp_disable(iva_dev, 660000000);
				opp_disable(iva_dev, 800000000);
			}
		}
	}
	return;
}

void omap_pm_dsp_set_min_opp(struct device *dev, unsigned long f)
{
	u8 opp_id;

	if (!dev) {
		WARN_ON(1);
		return;
	};

	pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);

if (cpu_is_omap3630()) {
		/*
		 * check if OPP requested is 65Mz or greater if yes set
		 * max opp constraint to OPP4, Which limits scaling of VDD1
		 * OPP to 1G only. 1.3G will be allowed when DSP load dies
		 * down to 65MHz.
		 */
		if ((f > S65M) && !vdd1_max_opp) {
			vdd1_max_opp = 1;
			omap_pm_vdd1_set_max_opp(dev, VDD1_OPP4);
			omap_pm_vdd1_set_max_opp(dev, VDD1_OPP5);
//			omap_pm_vdd1_set_max_opp(dev, VDD1_OPP6);
		} else if ((f < S260M) && vdd1_max_opp) {
			omap_pm_vdd1_set_max_opp(dev, 0);
			vdd1_max_opp = 0;
		}

		/*
		 * DSP table has 65MHz as OPP5, give OPP1-260MHz when DSP request
		 * 65MHz-OPP1
		 */
		if (f == S65M)
			f = S260M;
//			f = S520M;
	}

	opp_id = get_opp_id(dsp_opps + MAX_VDD1_OPP, f);

	/*
	 * For now pass a dummy_dev struct for SRF to identify the caller.
	 * Maybe its good to have DSP pass this as an argument
	 */
	resource_request("vdd1_opp", dev, opp_id);
	return;
}

static int __init beagle_opp_init(void)
{
	int r = 0;

	if (!machine_is_omap3_beagle())
		return 0;

	/* Initialize the omap3 opp table if not already created. */
	r = omap3_opp_init();
	if (r < 0 && (r != -EEXIST)) {
		pr_err("%s: opp default init failed\n", __func__);
		return r;
	}

	/* Custom OPP enabled for all xM versions */
	if (cpu_is_omap3630()) {
		struct device *mpu_dev, *iva_dev;

		mpu_dev = get_cpu_device(0);
		iva_dev = omap_device_get_by_hwmod_name("iva");

		if (!mpu_dev || IS_ERR(iva_dev)) {
			pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
				__func__, mpu_dev, iva_dev);
			return -ENODEV;
		}
		/* Enable MPU 1GHz and lower opps */
		r = dev_pm_opp_enable(mpu_dev, 800000000);
		/* TODO: MPU 1GHz needs SR and ABB */

		/* Enable IVA 800MHz and lower opps */
		r |= dev_pm_opp_enable(iva_dev, 660000000);
		/* TODO: DSP 800MHz needs SR and ABB */
		if (r) {
			pr_err("%s: failed to enable higher opp %d\n",
				__func__, r);
			/*
			 * Cleanup - disable the higher freqs - we dont care
			 * about the results
			 */
			dev_pm_opp_disable(mpu_dev, 800000000);
			dev_pm_opp_disable(iva_dev, 660000000);
		}
	}
	return 0;
}

static int sr_clk_enable(struct omap_sr *sr)
{
	if (clk_enable(sr->clk) != 0) {
		pr_err("Could not enable %s\n", sr->clk->name);
		return -1;
	}

	if (cpu_is_omap3630())
		sr_modify_reg(sr, ERRCONFIG_36XX, SR_IDLEMODE_MASK,
				SR_SMART_IDLE);
	else
	/* set fclk- active , iclk- idle */
	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
		      SR_CLKACTIVITY_IOFF_FON);

	return 0;
}

/*
 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 * @clk: struct clk * of DPLL to set
 * @m: DPLL multiplier to set
 * @n: DPLL divider to set
 * @freqsel: FREQSEL value to set
 *
 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 * lock..  Returns -EINVAL upon error, or 0 upon success.
 */
static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
{
	struct dpll_data *dd = clk->dpll_data;
	u32 v;

	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
	_omap3_noncore_dpll_bypass(clk);

	/* Set jitter correction. No jitter correction for OMAP4 and OMAP3630
	 * since those silicon do not have freqsel field */
	if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
		v = __raw_readl(dd->control_reg);
		v &= ~dd->freqsel_mask;
		v |= freqsel << __ffs(dd->freqsel_mask);
		__raw_writel(v, dd->control_reg);
	}

	/* Set DPLL multiplier, divider */
	v = __raw_readl(dd->mult_div1_reg);
	v &= ~(dd->mult_mask | dd->div1_mask);
	v |= m << __ffs(dd->mult_mask);
	v |= (n - 1) << __ffs(dd->div1_mask);
	__raw_writel(v, dd->mult_div1_reg);

	/*
	 * XXX This code is not needed for 3430/AM35XX; can it be optimized
	 * out in non-multi-OMAP builds for those chips?
	 */
	if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) {
		u8 dco, sd_div;
		lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
		/* XXX This probably will need revision for OMAP4 */
		v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
				| OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
		v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK);
		v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
	}

	/* We let the clock framework set the other output dividers later */

	/* REVISIT: Set ramp-up delay? */

	_omap3_noncore_dpll_lock(clk);

	return 0;
}

int __init omap_twl_init(void)
{
	struct omap_pmic_description *desc = NULL;

	/* Reuse OMAP3430 values */
	if (cpu_is_omap3630()) {
		omap3_mpu_pmic.min_volt = OMAP3630_VP1_VLIMITTO_VDDMIN;
		omap3_mpu_pmic.max_volt = OMAP3630_VP1_VLIMITTO_VDDMAX;
		omap3_core_pmic.min_volt = OMAP3630_VP2_VLIMITTO_VDDMIN;
		omap3_core_pmic.max_volt = OMAP3630_VP2_VLIMITTO_VDDMAX;
	}

	if (cpu_is_omap44xx())
		desc = &twl6030_pmic_desc;

	if (cpu_is_omap443x() && is_twl6030_lite()) {
		omap443x_core_pmic.volt_reg_addr
			= TWL6032_SMPS2_SR_VOLT_REG;
		omap443x_core_pmic.cmd_reg_addr
			= TWL6032_SMPS2_SR_CMD_REG;

		omap443x_446x_iva_pmic.volt_reg_addr
			= TWL6032_SMPS5_SR_VOLT_REG;
		omap443x_446x_iva_pmic.cmd_reg_addr
			= TWL6032_SMPS5_SR_CMD_REG;
		pr_info("%s: TWL6032 PMIC SR Addr Change Success!!\n",
				__func__);
	}
	if (cpu_is_omap446x() && is_twl6030_lite()) {
		omap446x_core_pmic.volt_reg_addr =
			TWL6032_SMPS2_SR_VOLT_REG;
		omap446x_core_pmic.cmd_reg_addr =
			TWL6032_SMPS2_SR_CMD_REG;

		omap443x_446x_iva_pmic.volt_reg_addr
			= TWL6032_SMPS5_SR_VOLT_REG;
		omap443x_446x_iva_pmic.cmd_reg_addr
			= TWL6032_SMPS5_SR_CMD_REG;
		pr_info("%s: TWL6032 PMIC SR Addr Change Success!!\n",
				__func__);
	}

	return omap_pmic_register_data(omap_twl_map, desc);
}