//!
//! @brief This function sends nb_data bytes pointed to by ptr_buf on the specified pipe.
//!
//! @param pipe
//! @param nb_data
//! @param ptr_buf
//! @param handler Call-back function pointer
//!
//! @return bool: Status
//!
bool host_send_data_interrupt(uint8_t pipe, uint16_t nb_data, const void *ptr_buf, Pipe_handler *handler)
{
  bool sav_glob_int_en;

  if (it_pipe_str[pipe].enable) return false;

  if (!is_any_interrupt_pipe_active())
  {
    g_sav_int_sof_enable = Is_host_sof_interrupt_enabled();
    Host_enable_sof_interrupt();
  }
  it_pipe_str[pipe].enable = true;
  it_pipe_str[pipe].nb_byte_to_process = nb_data;
  it_pipe_str[pipe].nb_byte_processed = 0;
  it_pipe_str[pipe].ptr_buf = (void *)ptr_buf;
  it_pipe_str[pipe].handler = handler;
  it_pipe_str[pipe].timeout = 0;
  it_pipe_str[pipe].nak_timeout = NAK_SEND_TIMEOUT;

  if ((sav_glob_int_en = cpu_irq_is_enabled())) cpu_irq_disable();
  Host_reset_pipe(pipe);
  (void)Is_host_resetting_pipe(pipe);
  if (sav_glob_int_en) cpu_irq_enable();
  Host_configure_pipe_token(pipe, TOKEN_OUT);
  Host_ack_out_ready(pipe);
  Host_unfreeze_pipe(pipe);
  // Prepare data to be sent
  Host_reset_pipe_fifo_access(pipe);
  it_pipe_str[pipe].nb_byte_on_going = nb_data - host_write_p_txpacket(pipe, ptr_buf, nb_data, NULL);
  private_sof_counter = 0;          // Reset the counter in SOF detection subroutine
  it_pipe_str[pipe].timeout = 0;    // Refresh time-out counter
  if ((sav_glob_int_en = cpu_irq_is_enabled())) cpu_irq_disable();
  Host_ack_out_ready(pipe);
  Host_ack_stall(pipe);
  Host_ack_nak_received(pipe);
  (void)Is_host_nak_received(pipe);
  if (sav_glob_int_en) cpu_irq_enable();

  Host_enable_stall_interrupt(pipe);
  Host_enable_pipe_error_interrupt(pipe);
  #if NAK_TIMEOUT_ENABLE == ENABLE
  Host_enable_nak_received_interrupt(pipe);
  #endif
  Host_enable_out_ready_interrupt(pipe);
  Host_enable_pipe_interrupt(pipe);

  Host_send_out(pipe);              // Send the USB frame

  return true;
}

void sched_preempt(void)
{
    struct tcb *tcb;
    cpu_irq_disable();
    if(sched_tcb_now == NULL)
    {
        cpu_irq_enable();
        return;
    }
    if(sched_tcb_now->state != TCB_STATE_RUNNING)
    {
        cpu_irq_enable();
        return;
    }
    if(sched_list_ready.head == NULL)
    {
        cpu_irq_enable();
        return;
    }
    tcb = sched_list_ready.head->tcb;
    if(tcb->prio < sched_tcb_now->prio)
    {
        cpu_irq_enable();
        return;
    }
    sched_tcb_ready(sched_tcb_now);
    sched_tcb_run(tcb);
    cpu_irq_enable();
}

/** \brief Main function.
 */
int main(void)
{
	/* Initialize the board.
	 * The board-specific conf_board.h file contains the configuration of
	 * the board initialization.
	 */
	sysclk_init();
	board_init();

	/* Disable Global interrupt */
	cpu_irq_disable();

    /* Set Interrupt CallBack Function **/
    ext_int_set_interrupt_callback(BUTTON_INTERRUPT_SOURCE,ext_int_callback);
	
	/* Enable the Ext Int */
	ext_int_init(BUTTON_INTERRUPT_SOURCE, BUTTON_INTERRUPT_MODE);

	/* Enable Global interrupt */
	cpu_irq_enable();

	/* Infinite loop and waiting for the external interrupt to occur */
	while (1) {
	}
}

int twi_master_init(volatile avr32_twi_t *twi, const twi_options_t *opt)
{
	irqflags_t flags = sysreg_read(AVR32_SR);
	int status = TWI_SUCCESS;

	// Set pointer to TWIM instance for IT
	twi_inst = twi;

	// Disable TWI interrupts
	cpu_irq_disable();
	twi->idr = ~0UL;
	twi->sr;

	// Reset TWI
	twi->cr = AVR32_TWI_CR_SWRST_MASK;
	cpu_irq_restore(flags);

	// Dummy read in SR
	twi->sr;

	// register Register twim_master_interrupt_handler interrupt
	// on level CONF_TWI_IRQ_LEVEL
	flags = cpu_irq_save();
	irq_register_handler(&twi_master_interrupt_handler, CONF_TWI_IRQ_LINE,
			CONF_TWI_IRQ_LEVEL);
	cpu_irq_restore(flags);

	// Select the speed
	twi_set_speed(twi, opt->speed, opt->pba_hz);

	// Probe the component
	//status = twi_probe(twi, opt->chip);

	return status;
}

// Switch into boot mode and reset
void EraseAndReset()
{
	cpu_irq_disable();

#if SAM4S
# define IFLASH_ADDR				IFLASH0_ADDR
# define IFLASH_PAGE_SIZE			IFLASH0_PAGE_SIZE
# define IFLASH_NB_OF_PAGES			(IFLASH0_SIZE / IFLASH_PAGE_SIZE)
#endif

#if SAM3XA
# define IFLASH_ADDR				IFLASH0_ADDR
# define IFLASH_PAGE_SIZE			IFLASH0_PAGE_SIZE
# define IFLASH_NB_OF_PAGES			((IFLASH1_ADDR + IFLASH1_SIZE - IFLASH_ADDR) / IFLASH_PAGE_SIZE)
#endif

    for(size_t i = 0; i <= IFLASH_NB_OF_PAGES; i++)
    {
    	wdt_restart(WDT);
        size_t pageStartAddr = IFLASH_ADDR + i * IFLASH_PAGE_SIZE;
        flash_unlock(pageStartAddr, pageStartAddr + IFLASH_PAGE_SIZE - 1, nullptr, nullptr);
    }

    flash_clear_gpnvm(1);			// tell the system to boot from ROM next time
	rstc_start_software_reset(RSTC);
	for(;;) {}
}

// control / network / logic init
static void init_ctl(void) {
  // disable interrupts
  cpu_irq_disable();

  // intialize the event queue
  init_events();
  print_dbg("\r\n init_events");

  // intialize encoders
  print_dbg("\r\n init_encoders");
  init_encoders();

  // send ADC config
  print_dbg("\r\n init_adc");
  init_adc();

  // start timers
  print_dbg("\r\n init_sys_timers");
  init_sys_timers();
  //  init_app_timers();

  // enable interrupts
  cpu_irq_enable();

}

USART_HOST_ISR_VECT()
#endif
{
	uint8_t temp;
#if SAMD || SAMR21 || SAML21
	usart_serial_read_packet(&host_uart_module, &temp, 1);
#else
	usart_serial_read_packet(USART_HOST, &temp, 1);
#endif

	/* Introducing critical section to avoid buffer corruption. */
	cpu_irq_disable();

	/* The number of data in the receive buffer is incremented and the
	 * buffer is updated. */

	serial_rx_buf[serial_rx_buf_tail] = temp;

	if ((SERIAL_RX_BUF_SIZE_HOST - 1) == serial_rx_buf_tail) {
		/* Reached the end of buffer, revert back to beginning of
		 * buffer. */
		serial_rx_buf_tail = 0x00;
	} else {
		serial_rx_buf_tail++;
	}

	cpu_irq_enable();
}

static void app_task(void)
{
	if (tx_state == TX_IDLE) {
		/* If bytes are received via USB, transmit the bytes.  */
		if (usb_rx_buff_len > 0) {
			tx_state = TX_ONGOING;

			/* Introducing critical section to avoid buffer corruption. */
			cpu_irq_disable();

			/* Check for maximum allowed frame length as per IEEE 802.15.4. */
			if (usb_rx_buff_len > (PHY_MAX_LENGTH - FCS_LEN)) {
				usb_rx_buff_len = PHY_MAX_LENGTH - FCS_LEN;
			}

			/* Update ppdu length within frame. */
			tx_buffer[0] = usb_rx_buff_len + FCS_LEN;

			/*
			 * Copy PSDU (actual PHY payload) into frame.
			 * Length of frame has to be first byte during transmission.
			*/
			memcpy(&tx_buffer[1], usb_rx_buffer, usb_rx_buff_len);
			usb_rx_buff_len = 0;

			cpu_irq_enable();

			/* AT86RFx API to transmit the frame. */
			at86rfx_tx_frame(tx_buffer);
		}
	}
}

static void usb_task(void)
{
	if (main_b_cdc_enable) {
		/* Check for any previous call back for Rx from USB. */
		if (usb_rx_byte_rcvd) {
			/* Loop to get all the bytes from the USB to application buffer. */
			while (udi_cdc_is_rx_ready()) {
				uint8_t temp;
				temp = udi_cdc_getc();

				/* Introducing critical section to avoid buffer corruption. */
				cpu_irq_disable();

				usb_rx_buffer[usb_rx_buff_len] = temp;
				usb_rx_buff_len++;

				cpu_irq_enable();

				if (usb_rx_buff_len >= BUFFER_SIZE) {
					break;
				}
			}
			/* Restore the flag after successful copy to application buffer. */
			usb_rx_byte_rcvd = false;
		}
	}
}

int8_t  i2c_driver_reset(uint8_t  i2c_device) 
{
	volatile avr32_twim_t *twim;
	
	switch (i2c_device) 
	{
		case 0: 
			twim = &AVR32_TWIM0;
		break;
		case 1:
			twim = &AVR32_TWIM1;
		break;
		default: // invalid device ID
			return -1;
	}		
	bool global_interrupt_enabled = cpu_irq_is_enabled ();
	// Disable TWI interrupts
	if (global_interrupt_enabled) 
	{
		cpu_irq_disable ();
	}
	twim->idr = ~0UL;
	// Enable master transfer
	twim->cr = AVR32_TWIM_CR_MEN_MASK;
	// Reset TWI
	twim->cr = AVR32_TWIM_CR_SWRST_MASK;
	if (global_interrupt_enabled) 
	{
		cpu_irq_enable ();
	}
	// Clear SR
	twim->scr = ~0UL;
}

/**
 * \brief Test interrupt is getting triggered in various Sleep mode.
 *
 * This function put the device in Idle and Power Save sleep mode and check
 * whether the ADC conversion complete interrupt is executed only in Idle sleep
 * mode.
 * The device will wakeup from power save mode when Timer/Counter2 overflow
 * occur.
 *
 * \param test Current test case.
 */
static void run_sleep_trigger_test(const struct test_case *test)
{
    /* Disable Global interrupt */
    cpu_irq_disable();
    /* Initialize the lock counts */
    sleepmgr_init();
    /* Initialize the ADC */
    adc_initialisation();
    /* Initialize the Timer/Counter2 */
    timer2_initialisation();
    /* Lock Idle Sleep mode */
    sleepmgr_lock_mode(SLEEPMGR_IDLE);
    /* Clear Timer/Counter2 Register */
    TCNT2 = 0;
    /* Wait for TCNT2 register to get updated */
    while (ASSR & (1 << TCN2UB)) {
    }
    /* Start ADC Conversion */
    adc_start_conversion();
    /* Enable Global interrupt */
    cpu_irq_enable();
    /* Go to sleep in the deepest allowed mode */
    sleepmgr_enter_sleep();
    /* Unlock Idle Sleep mode */
    sleepmgr_unlock_mode(SLEEPMGR_IDLE);
    /* Lock Power Save mode */
    sleepmgr_lock_mode(SLEEPMGR_PSAVE);
    /* Clear Timer/Counter2 Register */
    TCNT2 = 0;
    /* Wait for TCNT2 register to get updated */
    while (ASSR & (1 << TCN2UB)) {
    }
    /* Start ADC Conversion */
    adc_start_conversion();
    /* Go to sleep in the deepest allowed mode */
    sleepmgr_enter_sleep();
    /* Disable ADC */
    adc_disable();
    /* Unlock Power Save mode */
    sleepmgr_unlock_mode(SLEEPMGR_PSAVE);

    /* Disable Global interrupt */
    cpu_irq_disable();

    test_assert_true(test, trigger_count == 2,
                     "ADC interrupt trigger failed.");
}

void isp_start_appli(void)
{
	cpu_irq_disable();
	// generate soft reset for Xmega
	start_app_key=0x55AA;
	ccp_write_io((uint8_t *)&RST.CTRL, RST.CTRL | RST_SWRST_bm);
	while (1);
}

void pm_bod_disable_irq(volatile avr32_pm_t *pm)
{
  bool global_interrupt_enabled = cpu_irq_is_enabled();

  if (global_interrupt_enabled) cpu_irq_disable();
  pm->idr = AVR32_PM_IDR_BODDET_MASK;
  pm->isr;
  if (global_interrupt_enabled) cpu_irq_enable();
}

void rtc_clear_interrupt(volatile avr32_rtc_t *rtc)
{
  bool global_interrupt_enabled = cpu_irq_is_enabled();

  if (global_interrupt_enabled) cpu_irq_disable();
  rtc->icr = AVR32_RTC_ICR_TOPI_MASK;
  rtc->isr;
  if (global_interrupt_enabled) cpu_irq_enable();
}

void controller_shutdown(void)
{
  // Disable all interrupts
  cpu_irq_disable();
  // Disable the RTC
  rtc_disable(&AVR32_RTC);
  // Enable global interrupts
  cpu_irq_enable();
}

void app_cpu_load_enter_sleep(void)
{
	/* Disable all interrupts to avoid interrupt
	 * before enter the CPU in sleep mode */
	cpu_irq_disable();
	app_cpu_load_sleep = true;
	app_cpu_load_time_active += tc45_read_count(&TCC4);
	/* Reset Timer counter */
	tc45_write_count(&TCC4, 0);
}

void pmc_wait_wakeup_clocks_restore(
		pmc_callback_wakeup_clocks_restored_t callback)
{
	if (b_is_sleep_clock_used) {
		cpu_irq_disable();
		callback_clocks_restored = callback;
	} else if (callback) {
		callback();
	}
}

uint8_t UartBuffer_GetChar(void)
{
	uint8_t c = 0;
	cpu_irq_disable();
	if ( UartBuffer_RxReady() ) {
		c = RxBuffer[RxOut];
		RxOut++;
	}
	cpu_irq_enable();
	return c;		
}

void UartBuffer_PutChar(uint8_t c)
{
	cpu_irq_disable();
	uint16_t out_next = (TxOut+1);
	if ( out_next != TxIn ) {
		TxBuffer[TxIn] = c;
		TxIn++;
	}
	UartBuffer_Interrupt();
	cpu_irq_enable();
}

/**
 * \brief Disable the TWI interrupts and clear its status register
 *
 * \param twim         Base address of the TWIM (i.e. &AVR32_TWI).
 */
void twim_disable_interrupt (volatile avr32_twim_t *twim)
{
	bool global_interrupt_enabled = cpu_irq_is_enabled ();
	if (global_interrupt_enabled) {
		cpu_irq_disable ();
	}
	// Clear the interrupt flags
	twim->idr = ~0UL;
	// Clear the status flags
	twim->scr = ~0UL;
}