static void int1_unmask(struct irq_data *d)
{
	u32 intmr1;

	intmr1 = clps_readl(INTMR1);
	intmr1 |= 1 << d->irq;
	clps_writel(intmr1, INTMR1);
}

static void int3_unmask(struct irq_data *d)
{
	u32 intmr3;

	intmr3 = clps_readl(INTMR3);
	intmr3 |= 1 << (d->irq - 32);
	clps_writel(intmr3, INTMR3);
}

static void int2_unmask(struct irq_data *d)
{
	u32 intmr2;

	intmr2 = clps_readl(INTMR2);
	intmr2 |= 1 << (d->irq - 16);
	clps_writel(intmr2, INTMR2);
}

static void int2_mask(unsigned int irq)
{
	u32 intmr2;

	intmr2 = clps_readl(INTMR2);
	intmr2 &= ~(1 << (irq - 16));
	clps_writel(intmr2, INTMR2);
}

static void int1_mask(unsigned int irq)
{
	u32 intmr1;

	intmr1 = clps_readl(INTMR1);
	intmr1 &= ~(1 << irq);
	clps_writel(intmr1, INTMR1);
}

int setup_cs43l42(void)
{
	volatile long u;
	volatile char port_d;

	printk("cs43l42: init dac\n");
	port_d = clps_readb(PDDR) & ~(SCL | SDA);
	
	/* enable codec_en# */
	reset_cs43l42();

	/* make SDA & SCL outputs */
	make_scl_sda_outputs();

	/*
	 * enable the two wire serial interface on the CS43L42
	 * by setting the CP_EN bit (bit 0) of register 1
	 */
	cs43l42_i2c_write(ADDR_CS43L42, CS43L42_PWRCTL, 0xd2);

	/* set the data format to left justified */
	cs43l42_i2c_write(ADDR_CS43L42, 0x0b, 0x02);

	/* power on the DAC */
	cs43l42_i2c_write(ADDR_CS43L42, CS43L42_PWRCTL, 0xd0);

	/* delay while the DAC initializes */
	for(u = 0; u < 15; u++)
		udelay(5);

	cs43l42_i2c_write(ADDR_CS43L42, 2, 0xf1);
	cs43l42_i2c_write(ADDR_CS43L42, 3, 0xf1);

#if 0
	cs43l42_dump_regs();
	printk("syscon1 %08x\n", clps_readl(SYSCON1));
	printk("syscon2 %08x\n", clps_readl(SYSCON2));
	printk("syscon3 %08x\n", clps_readl(SYSCON3));
#endif
	/* restore original port D value */
	port_d |= clps_readb(PDDR);
	clps_writeb(port_d, PDDR);
	printk("cs43l42: init dac complete\n");

	return 0;
}

static void __init clps711x_timer_init(void)
{
	struct timespec tv;
	unsigned int syscon;

	syscon = clps_readl(SYSCON1);
	syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
	clps_writel(syscon, SYSCON1);

	clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */

	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);

	tv.tv_nsec = 0;
	tv.tv_sec = clps_readl(RTCDR);
	do_settimeofday(&tv);
}

static void unmask_irq_int2(unsigned int irq)
{
	u32 intmr2;

	intmr2 = clps_readl(INTMR2);
	intmr2 |= 1 << (irq - 16);
	clps_writel(intmr2, INTMR2);
}

static void unmask_irq_int1(unsigned int irq)
{
	u32 intmr1;

	intmr1 = clps_readl(INTMR1);
	intmr1 |= 1 << irq;
	clps_writel(intmr1, INTMR1);
}

static void uart_clps711x_shutdown(struct uart_port *port)
{
	/* Free the interrupts */
	devm_free_irq(port->dev, TX_IRQ(port), port);
	devm_free_irq(port->dev, RX_IRQ(port), port);

	/* Disable the port */
	clps_writel(clps_readl(SYSCON(port)) & ~SYSCON_UARTEN, SYSCON(port));
}

MACHINE_END

static int guide_a07_hw_init(void)
{
	/* in cs[1] (the FPGA), set zero wait states, clkenb, and sqaen */
	u32 memcfg1 = 0xfc << 8;
	memcfg1 |= clps_readl(MEMCFG1);
	clps_writel(memcfg1, MEMCFG1);

	return 0;
}

static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
{
	unsigned int ubrlcr;

	ubrlcr = clps_readl(UBRLCR(port));
	if (break_state == -1)
		ubrlcr |= UBRLCR_BREAK;
	else
		ubrlcr &= ~UBRLCR_BREAK;
	clps_writel(ubrlcr, UBRLCR(port));
}

static int ep7211_close(struct sir_dev *dev)
{
	unsigned int syscon;

	/* Turn off the SIR encoder. */
	syscon = clps_readl(SYSCON1);
	syscon &= ~SYSCON1_SIREN;
	clps_writel(syscon, SYSCON1);

	return 0;
}

static void uart_clps711x_console_write(struct console *co, const char *c,
					unsigned n)
{
	struct clps711x_port *s = (struct clps711x_port *)co->data;
	struct uart_port *port = &s->port[co->index];
	u32 syscon;

	/* Ensure that the port is enabled */
	syscon = clps_readl(SYSCON(port));
	clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));

	uart_console_write(port, c, n, uart_clps711x_console_putchar);

	/* Wait for transmitter to become empty */
	while (clps_readl(SYSFLG(port)) & SYSFLG_UBUSY)
		barrier();

	/* Restore the uart state */
	clps_writel(syscon, SYSCON(port));
}

static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct tty_struct *tty = tty_port_tty_get(&port->state->port);
	unsigned int status, ch, flg;

	if (!tty)
		return IRQ_HANDLED;

	for (;;) {
		status = clps_readl(SYSFLG(port));
		if (status & SYSFLG_URXFE)
			break;

		ch = clps_readw(UARTDR(port));
		status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
		ch &= 0xff;

		port->icount.rx++;
		flg = TTY_NORMAL;

		if (unlikely(status)) {
			if (status & UARTDR_PARERR)
				port->icount.parity++;
			else if (status & UARTDR_FRMERR)
				port->icount.frame++;
			else if (status & UARTDR_OVERR)
				port->icount.overrun++;

			status &= port->read_status_mask;

			if (status & UARTDR_PARERR)
				flg = TTY_PARITY;
			else if (status & UARTDR_FRMERR)
				flg = TTY_FRAME;
			else if (status & UARTDR_OVERR)
				flg = TTY_OVERRUN;
		}

		if (uart_handle_sysrq_char(port, ch))
			continue;

		if (status & port->ignore_status_mask)
			continue;

		uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
	}

	tty_flip_buffer_push(tty);

	tty_kref_put(tty);

	return IRQ_HANDLED;
}

static void int2_ack(unsigned int irq)
{
	u32 intmr2;

	intmr2 = clps_readl(INTMR2);
	intmr2 &= ~(1 << (irq - 16));
	clps_writel(intmr2, INTMR2);

	switch (irq) {
	case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
	}
}

static void int2_ack(struct irq_data *d)
{
	u32 intmr2;

	intmr2 = clps_readl(INTMR2);
	intmr2 &= ~(1 << (d->irq - 16));
	clps_writel(intmr2, INTMR2);

	switch (d->irq) {
	case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
	}
}

/*
 *	Print a string to the serial port trying not to disturb
 *	any possible real use of the port...
 *
 *	The console_lock must be held when we get here.
 *
 *	Note that this is called with interrupts already disabled
 */
static void
clps711xuart_console_write(struct console *co, const char *s,
			   unsigned int count)
{
	struct uart_port *port = clps711x_ports + co->index;
	unsigned int status, syscon;
	int i;

	/*
	 *	Ensure that the port is enabled.
	 */
	syscon = clps_readl(SYSCON(port));
	clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));

	/*
	 *	Now, do each character
	 */
	for (i = 0; i < count; i++) {
		do {
			status = clps_readl(SYSFLG(port));
		} while (status & SYSFLG_UTXFF);
		clps_writel(s[i], UARTDR(port));
		if (s[i] == '\n') {
			do {
				status = clps_readl(SYSFLG(port));
			} while (status & SYSFLG_UTXFF);
			clps_writel('\r', UARTDR(port));
		}
	}

	/*
	 *	Finally, wait for transmitter to become empty
	 *	and restore the uart state.
	 */
	do {
		status = clps_readl(SYSFLG(port));
	} while (status & SYSFLG_UBUSY);

	clps_writel(syscon, SYSCON(port));
}

static void ep7211_ir_open(dongle_t *self, struct qos_info *qos)
{
	unsigned int syscon1, flags;

	spin_lock_irqsave(&ep7211_lock, flags);

	/* Turn on the SIR encoder. */
	syscon1 = clps_readl(SYSCON1);
	syscon1 |= SYSCON1_SIREN;
	clps_writel(syscon1, SYSCON1);

	/* XXX: We should disable modem status interrupts on the first
		UART (interrupt #14). */

	spin_unlock_irqrestore(&ep7211_lock, flags);
}

static void ep7211_ir_close(dongle_t *self)
{
	unsigned int syscon1, flags;

	spin_lock_irqsave(&ep7211_lock, flags);

	/* Turn off the SIR encoder. */
	syscon1 = clps_readl(SYSCON1);
	syscon1 &= ~SYSCON1_SIREN;
	clps_writel(syscon1, SYSCON1);

	/* XXX: If we've disabled the modem status interrupts, we should
		reset them back to their original state. */

	spin_unlock_irqrestore(&ep7211_lock, flags);
}