static struct clk *twd_get_clock(void)
{
	struct clk *clk;
	int err;

	clk = clk_get_sys("smp_twd", NULL);
	if (IS_ERR(clk)) {
		pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
		return clk;
	}

	err = clk_prepare(clk);
	if (err) {
		pr_err("smp_twd: clock failed to prepare: %d\n", err);
		clk_put(clk);
		return ERR_PTR(err);
	}

	err = clk_enable(clk);
	if (err) {
		pr_err("smp_twd: clock failed to enable: %d\n", err);
		clk_unprepare(clk);
		clk_put(clk);
		return ERR_PTR(err);
	}

	return clk;
}

static int clk_set_rate_clk81(struct clk *clk, unsigned long rate)
{
    unsigned long r = rate;
    struct clk *father_clk;
    unsigned long r1;
    int ret;
	
    if (r < 1000)
        r = r * 1000000;

    father_clk = clk_get_sys("clk_other_pll", NULL);

    r1 = clk_get_rate(father_clk);

    if (r1 != r*4) {
        ret = father_clk->set_rate(father_clk, r*4);

        if (ret != 0)
            return ret;
    }

    clk->rate = r;

    WRITE_MPEG_REG(HHI_MPEG_CLK_CNTL,
              (1 << 12) |          // select other PLL
              ((4 - 1) << 0 ) |    // div1
              (1 << 7 ) |          // cntl_hi_mpeg_div_en, enable gating
              (1 << 8 ));          // Connect clk81 to the PLL divider output

    return 0;
}

static struct tegra_emc_pdata *tegra_emc_fill_pdata(struct platform_device *pdev)
{
	struct clk *c = clk_get_sys(NULL, "emc");
	struct tegra_emc_pdata *pdata;
	unsigned long khz;
	int i;

	WARN_ON(pdev->dev.platform_data);
	BUG_ON(IS_ERR(c));

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
				     GFP_KERNEL);

	pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000;

	for (i = 0; i < TEGRA_EMC_NUM_REGS; i++)
		pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]);

	pdata->num_tables = 1;

	khz = pdata->tables[0].rate;
	dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, "
		 "%ld kHz mem\n", khz * 2, khz);

	return pdata;
}

static void dmb_pmic_xo_onoff(int on)
{

 int rc=0;

  if(!xo_handle_a2)
  {
      xo_handle_a2 = clk_get_sys("dmb_clk", "xo");
      if (IS_ERR(xo_handle_a2))
       DMB_MSG_HW("[%s] clk_get err \n", __func__);
   }
   
 

  if(on)
  {
     rc = clk_prepare_enable(xo_handle_a2);
     if(rc != 0)
       DMB_MSG_HW("[%s] clk_prepare_enable err [%d]\n", __func__, rc);
  }
  else
  {
     clk_disable_unprepare(xo_handle_a2);
  }
  if (rc < 0)
  {
    DMB_MSG_HW("[%s] Configuring dmb_pmic_xo_onoff failed (%d)\n", __func__, rc);
    return;
  }    
  return;
}

static int clk_set_rate_a9_clk(struct clk *clk, unsigned long rate)
{
	unsigned long r = rate;
	struct clk *father_clk;
	unsigned long r1;
	int ret;

	if (r < 1000)
		r = r * 1000000;

	father_clk = clk_get_sys("clk_sys_pll", NULL);

	r1 = clk_get_rate(father_clk);

	if (!r1)
		return -1;

	if (r1!=r*2 && r!=0) {
		ret = father_clk->set_rate(father_clk, r*2);

		if (ret != 0)
			return ret;
	}

	clk->rate = r;

	WRITE_MPEG_REG(HHI_A9_CLK_CNTL,
		(0 << 10) |	   // 0 - sys_pll_clk, 1 - audio_pll_clk
		(1 << 0 ) |	   // 1 - sys/audio pll clk, 0 - XTAL
		(1 << 4 ) |	   // APB_CLK_ENABLE
		(1 << 5 ) |	   // AT_CLK_ENABLE
		(0 << 2 ) |	   // div1
		(1 << 7 ));	   // Connect A9 to the PLL divider output
	return 0;
}

/**
 * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
 * @od: struct omap_device *od
 *
 * For every optional clock present per hwmod per omap_device, this function
 * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
 * if it does not exist already.
 *
 * The function is called from inside omap_device_build_ss(), after
 * omap_device_register.
 *
 * This allows drivers to get a pointer to its optional clocks based on its role
 * by calling clk_get(<dev*>, <role>).
 *
 * No return value.
 */
static void _add_optional_clock_clkdev(struct omap_device *od,
				      struct omap_hwmod *oh)
{
	int i;

	for (i = 0; i < oh->opt_clks_cnt; i++) {
		struct omap_hwmod_opt_clk *oc;
		struct clk *r;
		struct clk_lookup *l;

		oc = &oh->opt_clks[i];

		if (!oc->_clk)
			continue;

		r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
		if (!IS_ERR(r))
			continue; /* clkdev entry exists */

		r = omap_clk_get_by_name((char *)oc->clk);
		if (IS_ERR(r)) {
			pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
			       dev_name(&od->pdev.dev), oc->clk);
			continue;
		}

		l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
		if (!l) {
			pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
			       dev_name(&od->pdev.dev), oc->role);
			return;
		}
		clkdev_add(l);
	}
}

static void __init uart_debug_init(void)
{
	int debug_port_id;
	struct platform_device *debug_uart;

	debug_port_id = get_tegra_uart_debug_port_id();
	if (debug_port_id < 0) {
		debug_port_id = 3;
	} else if (debug_port_id >= ARRAY_SIZE(debug_uarts)) {
		pr_info("The debug console id %d is invalid, Assuming UARTA",
			debug_port_id);
		debug_port_id = 0;
	}

	pr_info("Selecting %s as the debug port\n",
		uart_names[debug_port_id]);
	debug_uart_clk = clk_get_sys("serial8250.0",
				     uart_names[debug_port_id]);
	debug_uart = debug_uarts[debug_port_id];
	debug_uart_port_base = ((struct plat_serial8250_port *)(
			debug_uart->dev.platform_data))->mapbase;
	debug_uart_port_irq = ((struct plat_serial8250_port *)(
			debug_uart->dev.platform_data))->irq;
	return;
}

static void __init spear3xx_timer_init(void)
{
	char pclk_name[] = "pll3_clk";
	struct clk *gpt_clk, *pclk;

	spear3xx_clk_init();

	/* get the system timer clock */
	gpt_clk = clk_get_sys("gpt0", NULL);
	if (IS_ERR(gpt_clk)) {
		pr_err("%s:couldn't get clk for gpt\n", __func__);
		BUG();
	}

	/* get the suitable parent clock for timer*/
	pclk = clk_get(NULL, pclk_name);
	if (IS_ERR(pclk)) {
		pr_err("%s:couldn't get %s as parent for gpt\n",
				__func__, pclk_name);
		BUG();
	}

	clk_set_parent(gpt_clk, pclk);
	clk_put(gpt_clk);
	clk_put(pclk);

	spear_setup_of_timer();
}

static int tegra_usb_phy_get_clocks(struct tegra_usb_phy *phy)
{
	int err = 0;

	phy->pllu_clk = clk_get_sys(NULL, "pll_u");
	if (IS_ERR(phy->pllu_clk)) {
		ERR("inst:[%d] Can't get pllu_clk clock\n", phy->inst);
		err = PTR_ERR(phy->pllu_clk);
		goto fail_pll;
	}
	clk_enable(phy->pllu_clk);

	phy->ctrlr_clk = clk_get(&phy->pdev->dev, NULL);
	if (IS_ERR(phy->ctrlr_clk)) {
		dev_err(&phy->pdev->dev, "Can't get controller clock\n");
		err = PTR_ERR(phy->ctrlr_clk);
		goto fail_ctrlr_clk;
	}

	if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
		if (phy->pdata->u_data.host.hot_plug ||
			phy->pdata->u_data.host.remote_wakeup_supported)
			clk_enable(phy->ctrlr_clk);

	phy->sys_clk = clk_get(&phy->pdev->dev, "sclk");
	if (IS_ERR(phy->sys_clk)) {
		dev_err(&phy->pdev->dev, "Can't get sclk clock\n");
		err = PTR_ERR(phy->sys_clk);
		goto fail_sclk;
	}
	clk_set_rate(phy->sys_clk, 80000000);

	phy->emc_clk = clk_get(&phy->pdev->dev, "emc");
	if (IS_ERR(phy->emc_clk)) {
		dev_err(&phy->pdev->dev, "Can't get emc clock\n");
		err = PTR_ERR(phy->emc_clk);
		goto fail_emc;
	}

	if(phy->pdata->has_hostpc)
		clk_set_rate(phy->emc_clk, 100000000);
	else
		clk_set_rate(phy->emc_clk, 300000000);

	return err;

fail_emc:
	clk_put(phy->sys_clk);

fail_sclk:
	clk_put(phy->ctrlr_clk);

fail_ctrlr_clk:
	clk_disable(phy->pllu_clk);
	clk_put(phy->pllu_clk);

fail_pll:
	return err;
}

void mop500_snowball_ethernet_clock_enable(void)
{
	struct clk *clk;

	clk = clk_get_sys("fsmc", NULL);
	if (!IS_ERR(clk))
		clk_prepare_enable(clk);
}

static void __init uart_debug_init(void)
{
	/* Use skuinfo to decide debug uart */
	/* UARTB is the debug port. */
	pr_info("Selecting UARTB as the debug console\n");
	p1852_uart_devices[1] = &debug_uartb_device;
	debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
}

int tegra_auto_hotplug_init(struct mutex *cpu_lock)
{
	/*
	 * Not bound to the issuer CPU (=> high-priority), has rescue worker
	 * task, single-threaded, freezable.
	 */
	hotplug_wq = alloc_workqueue(
		"cpu-tegra3", WQ_UNBOUND | WQ_RESCUER | WQ_FREEZABLE, 1);
	if (!hotplug_wq)
		return -ENOMEM;
	INIT_DELAYED_WORK(&hotplug_work, tegra_auto_hotplug_work_func);

	cpu_clk = clk_get_sys(NULL, "cpu");
	cpu_g_clk = clk_get_sys(NULL, "cpu_g");
	cpu_lp_clk = clk_get_sys(NULL, "cpu_lp");
	if (IS_ERR(cpu_clk) || IS_ERR(cpu_g_clk) || IS_ERR(cpu_lp_clk))
		return -ENOENT;

	idle_top_freq = clk_get_max_rate(cpu_lp_clk) / 1000;
	idle_bottom_freq = clk_get_min_rate(cpu_g_clk) / 1000;

	up2g0_delay = msecs_to_jiffies(UP2G0_DELAY_MS);
	up2gn_delay = msecs_to_jiffies(UP2Gn_DELAY_MS);
	down_delay = msecs_to_jiffies(DOWN_DELAY_MS);

	tegra3_cpu_lock = cpu_lock;
	hp_state = INITIAL_STATE;
	hp_init_stats();
	pr_info("Tegra auto-hotplug initialized: %s\n",
		(hp_state == TEGRA_HP_DISABLED) ? "disabled" : "enabled");

	if (pm_qos_add_notifier(PM_QOS_MIN_ONLINE_CPUS, &min_cpus_notifier))
		pr_err("%s: Failed to register min cpus PM QoS notifier\n",
			__func__);

	rt_cfg_kobj = kobject_create_and_add("rt_config", kernel_kobj);
	if (!rt_cfg_kobj) {
		pr_err("cpu_tegra3: failed to create sysfs rt_cfg_kobj object");
		return 0;
	}
	if (sysfs_create_files(rt_cfg_kobj, rt_cfg_attributes)) {
		pr_err("tegra3_dvfs: failed to create sysfs rt_cfg_kobj interface");
		return 0;
	}
	return 0;
}

int tegra_das_set_mclk_parent(int parent)
{
	/* FIXME ; set parent based on need */
	struct clk *mclk_source = clk_get_sys(NULL, "pll_a_out0");

	clk_set_parent(aud_manager->mclk, mclk_source);
	return 0;
}

void __init nmdk_timer_init(void)
{
	unsigned long rate;
	struct clk *clk0;
	u32 cr = MTU_CRn_32BITS;

	clk0 = clk_get_sys("mtu0", NULL);
	BUG_ON(IS_ERR(clk0));

	clk_enable(clk0);

	/*
	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	 * for ux500.
	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	 * with 16 gives too low timer resolution.
	 */
	rate = clk_get_rate(clk0);
	if (rate > 32000000) {
		rate /= 16;
		cr |= MTU_CRn_PRESCALE_16;
	} else {
		cr |= MTU_CRn_PRESCALE_1;
	}

	/* Timer 0 is the free running clocksource */
	writel(cr, mtu_base + MTU_CR(0));
	writel(0, mtu_base + MTU_LR(0));
	writel(0, mtu_base + MTU_BGLR(0));
	writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));

	/* Now the clock source is ready */
	nmdk_clksrc.read = nmdk_read_timer;

	if (clocksource_register_hz(&nmdk_clksrc, rate))
		pr_err("timer: failed to initialize clock source %s\n",
		       nmdk_clksrc.name);

	init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);

	/* Timer 1 is used for events */

	clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);

	writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */

	nmdk_clkevt.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
	nmdk_clkevt.min_delta_ns =
		clockevent_delta2ns(0x00000002, &nmdk_clkevt);
	nmdk_clkevt.cpumask	= cpumask_of(0);

	/* Register irq and clockevents */
	setup_irq(IRQ_MTU0, &nmdk_timer_irq);
	clockevents_register_device(&nmdk_clkevt);
}

int tvoutc_setclk(tvmode_t mode)
{
	struct clk *clk;
	const  reg_t *sd,*hd;
	int xtal;

	sd=tvreg_vclk_sd;
	hd=tvreg_vclk_hd;

	clk=clk_get_sys("clk_xtal", NULL);
	if(!clk)
	{
		printk(KERN_ERR "can't find clk %s for VIDEO PLL SETTING!\n\n","clk_xtal");
		return -1;
	}
	xtal=clk_get_rate(clk);
	xtal=xtal/1000000;
	if(xtal>=24 && xtal <=25)/*current only support 24,25*/
		{
		xtal-=24;
		}
	else
		{
		printk(KERN_WARNING "UNsupport xtal setting for vidoe xtal=%d,default to 24M\n",xtal);
		xtal=0;
		}
	switch(mode)
	{
		case TVMODE_480I:
		case TVMODE_480I_RPT:
		case TVMODE_480CVBS:
		case TVMODE_480P:
		case TVMODE_480P_RPT:
		case TVMODE_576I:
		case TVMODE_576I_RPT:
		case TVMODE_576CVBS:
		case TVMODE_576P:
			  setreg(&sd[xtal]);
			  break;
		case TVMODE_720P:
		case TVMODE_720P_50HZ:
		case TVMODE_1080I:
		case TVMODE_1080I_50HZ:
		case TVMODE_1080P:
		case TVMODE_1080P_50HZ:
			  setreg(&hd[xtal]);
			  if(xtal == 1)
			  {
				WRITE_MPEG_REG(HHI_VID_CLK_DIV, 4);
			  }
			  break;
		default:
			//printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
            break;
	}

	return 0 ;
}

static int rk1000_control_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
    int ret;
	struct clk *iis_clk;
	struct rkdisplay_platform_data *tv_data;
	/* reg[0x00] = 0x88, --> ADC_CON
	   reg[0x01] = 0x0d, --> CODEC_CON
	   reg[0x02] = 0x22, --> I2C_CON
	   reg[0x03] = 0x00, --> TVE_CON
	 */
	char data[4] = {0x88, 0x0d, 0x22, 0x00};
	
    printk("rk1000_control_probe\n");
    
    iis_clk = clk_get_sys("rk29_i2s.0", "i2s");
	if (IS_ERR(iis_clk)) {
		printk("failed to get i2s clk\n");
		ret = PTR_ERR(iis_clk);
	}else{
		DBG("got i2s clk ok!\n");
		clk_enable(iis_clk);
		clk_set_rate(iis_clk, 11289600);
		#ifdef CONFIG_ARCH_RK29
		rk29_mux_api_set(GPIO2D0_I2S0CLK_MIIRXCLKIN_NAME, GPIO2H_I2S0_CLK);
		#else
		rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME, GPIO0B_I2S_8CH_CLK);
		#endif
		clk_put(iis_clk);
	}
    
    if(client->dev.platform_data) {
		tv_data = client->dev.platform_data;
		if(tv_data->io_reset_pin != INVALID_GPIO) {
	    	ret = gpio_request(tv_data->io_reset_pin, "rk1000 reset");
		    if (ret){   
		        printk("rk1000_control_probe request gpio fail\n");
		        //goto err1;
		    }
		    
		    gpio_set_value(tv_data->io_reset_pin, GPIO_LOW);
		    gpio_direction_output(tv_data->io_reset_pin, GPIO_LOW);
		    mdelay(2);
		    gpio_set_value(tv_data->io_reset_pin, GPIO_HIGH);
		}
	}
    
    rk1000_control_client = client;

#ifdef CONFIG_SND_SOC_RK1000
    data[1] = 0x00;
#endif

	ret = i2c_master_reg8_send(client,0,data, 4, 20 * 1000);
	
	printk("rk1000_control_probe ok\n");
    return 0;
}

/*
 * mmio_clock_init() - Initialize clocks.
 *
 * This function is customizable.
 * It allows to get the clocks that will be used.
 * It is called from mmio_platform_init function.
 */
static int mmio_clock_init(struct mmio_platform_data *pdata)
{
	int err = 0;
	struct mmio_board_data *extra = pdata->extra;

	dev_dbg(pdata->dev, "Board %s() Enter\n", __func__);

	extra->clk_bml.clk_ptr = clk_get_sys(extra->clk_bml.name, NULL);
	if (IS_ERR(extra->clk_bml.clk_ptr)) {
		err = PTR_ERR(extra->clk_bml.clk_ptr);
		dev_err(pdata->dev, "Error %d getting clock '%s'\n",
				err,
				extra->clk_bml.name);
		goto err_bml_clk;
	}

	extra->clk_ipi2c.clk_ptr = clk_get_sys(extra->clk_ipi2c.name, NULL);
	if (IS_ERR(extra->clk_ipi2c.clk_ptr)) {
		err = PTR_ERR(extra->clk_ipi2c.clk_ptr);
		dev_err(pdata->dev, "Error %d getting clock '%s'\n",
				err,
				extra->clk_ipi2c.name);
		goto err_ipi2c_clk;
	}

	extra->clk_ext.clk_ptr = clk_get_sys(extra->clk_ext.name, NULL);
	if (IS_ERR(extra->clk_ext.clk_ptr)) {
		err = PTR_ERR(extra->clk_ext.clk_ptr);
		dev_err(pdata->dev, "Error %d getting clock '%s'\n",
				err,
				extra->clk_ext.name);
		goto err_ext_clk;
	}

	dev_dbg(pdata->dev, "Board %s() Exit\n", __func__);

	return err;

err_ext_clk:
	clk_put(extra->clk_ipi2c.clk_ptr);
err_ipi2c_clk:
	clk_put(extra->clk_bml.clk_ptr);
err_bml_clk:
	return err;
}

static void __init uart_debug_init(void)
{
	/* UARTA is the debug port. */
	pr_info("Selecting UARTA as the debug console\n");
	e1853_uart_devices[0] = &debug_uarta_device;
	debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
	debug_uart_port_base = ((struct plat_serial8250_port *)(
				debug_uarta_device.dev.platform_data))->mapbase;
}

static void __init mx53_evk_timer_init(void)
{
	struct clk *uart_clk;

	mx53_clocks_init(32768, 24000000, 22579200, 24576000);

	uart_clk = clk_get_sys("mxcintuart.0", NULL);
	early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk);
}

static void _add_clkdev(struct omap_device *od, const char *clk_alias,
		       const char *clk_name)
{
	struct clk *r;
	int rc;

	if (!clk_alias || !clk_name)
		return;

	dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);

	r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
	if (!IS_ERR(r)) {
		dev_dbg(&od->pdev->dev,
			 "alias %s already exists\n", clk_alias);
		clk_put(r);
		return;
	}

	r = clk_get_sys(NULL, clk_name);

	if (IS_ERR(r)) {
		struct of_phandle_args clkspec;

		clkspec.np = of_find_node_by_name(NULL, clk_name);

		r = of_clk_get_from_provider(&clkspec);

		rc = clk_register_clkdev(r, clk_alias,
					 dev_name(&od->pdev->dev));
	} else {
		rc = clk_add_alias(clk_alias, dev_name(&od->pdev->dev),
				   clk_name, NULL);
	}

	if (rc) {
		if (rc == -ENODEV || rc == -ENOMEM)
			dev_err(&od->pdev->dev,
				"clkdev_alloc for %s failed\n", clk_alias);
		else
			dev_err(&od->pdev->dev,
				"clk_get for %s failed\n", clk_name);
	}
}