static int
ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, uint8_t slave,
    uint8_t is_read)
{
	uint32_t err, fmhp, val;

	desc->control |= ISMT_DESC_FAIR;
	if (sc->using_msi)
		desc->control |= ISMT_DESC_INT;

	desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read);
	desc->dptr_low = (sc->dma_buffer_bus_addr & 0xFFFFFFFFLL);
	desc->dptr_high = (sc->dma_buffer_bus_addr >> 32);

	wmb();

	fmhp = sc->head << 16;
	val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL);
	val &= ~ISMT_MCTRL_FMHP;
	val |= fmhp;
	bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val);

	/* set the start bit */
	val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL);
	val |= ISMT_MCTRL_SS;
	bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val);

	err = tsleep(sc, PWAIT, "ismt_wait", 5 * hz);

	if (err != 0) {
		ISMT_DEBUG(sc->pcidev, "%s timeout\n", __func__);
		return (SMB_ETIMEOUT);
	}

	ISMT_DEBUG(sc->pcidev, "%s status=0x%x\n", __func__, desc->status);

	if (desc->status & ISMT_DESC_SCS)
		return (SMB_ENOERR);

	if (desc->status & ISMT_DESC_NAK)
		return (SMB_ENOACK);

	if (desc->status & ISMT_DESC_CRC)
		return (SMB_EBUSERR);

	if (desc->status & ISMT_DESC_COL)
		return (SMB_ECOLLI);

	if (desc->status & ISMT_DESC_LPR)
		return (SMB_EINVAL);

	if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
		return (SMB_ETIMEOUT);

	return (SMB_EBUSERR);
}

static int
ata_kauai_begin_transaction(struct ata_request *request)
{
	struct ata_kauai_softc *sc = device_get_softc(request->parent);

	bus_write_4(sc->sc_memr, UDMA_CONFIG_REG, sc->udmaconf[request->unit]);
	bus_write_4(sc->sc_memr, PIO_CONFIG_REG, 
	    sc->wdmaconf[request->unit] | sc->pioconf[request->unit]);

	return ata_begin_transaction(request);
}

static void
sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
		  uint32_t val)
{
	struct sdhci_fdt_softc *sc = device_get_softc(dev);
	bus_write_4(sc->mem_res[slot->num], off, val);
}

static void 
davbus_cint(void *ptr)
{
	struct davbus_softc *d = ptr;
	u_int	reg, status, mask;

	mtx_lock(&d->mutex);

	reg = bus_read_4(d->reg, DAVBUS_SOUND_CTRL);
	if (reg & DAVBUS_PORTCHG) {
		
		status = bus_read_4(d->reg, DAVBUS_CODEC_STATUS);
		
		if (d->read_status && d->set_outputs) {

			mask = (*d->read_status)(d, status);
			(*d->set_outputs)(d, mask);
		}

		/* Clear the interrupt. */
		bus_write_4(d->reg, DAVBUS_SOUND_CTRL, reg);
	}

	mtx_unlock(&d->mutex);
}

static int
terasic_mtl_reg_write(struct cdev *dev, struct uio *uio, int flag)
{
	struct terasic_mtl_softc *sc;
	u_long offset, size;
	uint32_t v;
	int error;

	if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 ||
	    uio->uio_resid % 4 != 0)
		return (ENODEV);
	sc = dev->si_drv1;
	size = rman_get_size(sc->mtl_reg_res);
	error = 0;
	while (uio->uio_resid > 0) {
		offset = uio->uio_offset;
		if (offset + sizeof(v) > size)
			return (ENODEV);
		error = uiomove(&v, sizeof(v), uio);
		if (error)
			return (error);
		bus_write_4(sc->mtl_reg_res, offset, v);
	}
	return (error);
}

/**
 * Write a data item to the bridged address space at the given @p offset from
 * @p addr.
 *
 * A dynamic register window will be used to map @p addr.
 * 
 * @param probe		The bhndb_pci probe state to be used to perform the
 *			write.
 * @param addr		The base address.
 * @param offset	The offset from @p addr at which @p value will be
 *			written.
 * @param value		The data item to be written.
 * @param width		The data item width (1, 2, or 4 bytes).
 */
static void
bhndb_pci_probe_write(struct bhndb_pci_probe *probe, bhnd_addr_t addr,
    bhnd_size_t offset, uint32_t value, u_int width)
{
	struct resource	*r;
	bus_size_t	 res_offset;
	int		 error;

	/* Map the target address */
	error = bhndb_pci_probe_map(probe, addr, offset, width, &r,
	    &res_offset);
	if (error) {
		device_printf(probe->dev, "error mapping %#jx+%#jx for "
		    "writing: %d\n", addr, offset, error);
		return;
	}

	/* Perform write */
	switch (width) {
	case 1:
		return (bus_write_1(r, res_offset, value));
	case 2:
		return (bus_write_2(r, res_offset, value));
	case 4:
		return (bus_write_4(r, res_offset, value));
	default:
		panic("unsupported width: %u", width);
	}
}

/**
 * Write a 1, 2, or 4 byte data item to the PCI core's registers at @p offset.
 * 
 * @param sc		bhndb PCI driver state.
 * @param offset	register write offset.
 * @param value		value to be written.
 * @param width		item width (1, 2, or 4 bytes).
 */
static void
bhndb_pci_write_core(struct bhndb_pci_softc *sc, bus_size_t offset,
    uint32_t value, u_int width)
{
	struct resource	*r;
	bus_size_t	 r_offset;
	int		 error;

	error = bhndb_pci_get_core_regs(sc, offset, width, &r, &r_offset);
	if (error) {
		panic("no PCI register window mapping %#jx+%#x: %d",
		    (uintmax_t)offset, width, error);
	}

	switch (width) {
	case 1:
		bus_write_1(r, r_offset, value);
		break;
	case 2:
		bus_write_2(r, r_offset, value);
		break;
	case 4:
		bus_write_4(r, r_offset, value);
		break;
	default:
		panic("invalid width: %u", width);
	}
}

/*
 * Configure all PLL counter parameters.
 */
static int
altpll_write_params(struct altpll_softc *sc, uint32_t mul, uint32_t div,
     uint32_t c0)
{
	uint32_t status;
	int retry;

	altpll_write_param(sc, ALTPLL_OFF_TYPE_N, div);
	altpll_write_param(sc, ALTPLL_OFF_TYPE_M, mul);
	altpll_write_param(sc, ALTPLL_OFF_TYPE_C0, c0);
	/*
	 * Program C1 with the same parameters as C0. It seems the PLL does not
	 * run correctly otherwise.
	 */
	altpll_write_param(sc, ALTPLL_OFF_TYPE_C1, c0);
	/* Trigger the transfer. */
	bus_write_4(sc->ap_reg_res, ALTPLL_OFF_TRANSFER, htole32(0xff));
	/* Wait for the transfer to complete. */
	status = bus_read_4(sc->ap_reg_res, ALTPLL_OFF_TRANSFER);
	for (retry = 0;
	    status != htole32(ALTPLL_TRANSFER_COMPLETE) && retry < 10; retry++)
		status = bus_read_4(sc->ap_reg_res, ALTPLL_OFF_TRANSFER);
	if (status != htole32(ALTPLL_TRANSFER_COMPLETE)) {
		device_printf(sc->ap_dev,
		    "timed out waiting for transfer to PLL\n");
		/* XXXEM ignore error for now - not set by old FPGA bitfiles. */
	}

	return (0);
}

static inline void
am335x_dmtimer_et_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
    uint32_t val)
{

	bus_write_4(sc->et_memres, reg, val);
}

static void
le_dma_hwreset(struct lance_softc *sc)
{
	struct le_dma_softc *lesc = (struct le_dma_softc *)sc;
	struct lsi64854_softc *dma = lesc->sc_dma;
	uint32_t aui_bit, csr;

	/*
	 * Reset DMA channel.
	 */
	csr = L64854_GCSR(dma);
	aui_bit = csr & E_TP_AUI;
	DMA_RESET(dma);

	/* Write bits 24-31 of Lance address. */
	bus_write_4(dma->sc_res, L64854_REG_ENBAR,
	    lesc->sc_laddr & 0xff000000);

	DMA_ENINTR(dma);

	/*
	 * Disable E-cache invalidates on chip writes.
	 * Retain previous cable selection bit.
	 */
	csr = L64854_GCSR(dma);
	csr |= (E_DSBL_WR_INVAL | aui_bit);
	L64854_SCSR(dma, csr);
	DELAY(20000);	/* We must not touch the LANCE chip for 20ms. */
}

static int
mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val)
{

	bus_write_4(sc->res[0], off, val);
	return (0);
}

static int
macgpio_resume(device_t dev)
{
	struct macgpio_softc *sc;
	int i;

	sc = device_get_softc(dev);
	bus_write_4(sc->sc_gpios, GPIO_LEVELS_0, sc->sc_saved_gpio_levels[0]);
	bus_write_4(sc->sc_gpios, GPIO_LEVELS_1, sc->sc_saved_gpio_levels[1]);

	for (i = 0; i < GPIO_COUNT; i++)
		bus_write_1(sc->sc_gpios, GPIO_BASE + i, sc->sc_saved_gpios[i]);
	for (i = 0; i < GPIO_EXTINT_COUNT; i++)
		bus_write_1(sc->sc_gpios, GPIO_EXTINT_BASE + i, sc->sc_saved_extint_gpios[i]);

	return (0);
}

void
imx6_anatop_write_4(bus_size_t offset, uint32_t value)
{

	KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL"));

	bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);
}

void
terasic_mtl_reg_textframebufaddr_set(struct terasic_mtl_softc *sc,
    uint32_t addr)
{

	addr = htole32(addr);
	bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR, addr);
}

static int
usbphy_utmi_disable(struct usbphy_softc *sc)
{
	int rv;
	uint32_t val;

	usbphy_utmi_phy_clk(sc, false);

	if (sc->dr_mode == USB_DR_MODE_DEVICE) {
		val = RD4(sc, IF_USB_SUSP_CTRL);
		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
		val |= USB_WAKE_ON_CNNT_EN_DEV;
		val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
		WR4(sc, IF_USB_SUSP_CTRL, val);
	}

	val = RD4(sc, IF_USB_SUSP_CTRL);
	val |= UTMIP_RESET;
	WR4(sc, IF_USB_SUSP_CTRL, val);

	val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
	val |= UTMIP_PD_CHRG;
	WR4(sc, UTMIP_BAT_CHRG_CFG0, val);

	val = RD4(sc, UTMIP_XCVR_CFG0);
	val |= UTMIP_FORCE_PD_POWERDOWN;
	val |= UTMIP_FORCE_PD2_POWERDOWN;
	val |= UTMIP_FORCE_PDZI_POWERDOWN;
	WR4(sc, UTMIP_XCVR_CFG0, val);

	val = RD4(sc, UTMIP_XCVR_CFG1);
	val |= UTMIP_FORCE_PDDISC_POWERDOWN;
	val |= UTMIP_FORCE_PDCHRP_POWERDOWN;
	val |= UTMIP_FORCE_PDDR_POWERDOWN;
	WR4(sc, UTMIP_XCVR_CFG1, val);

	usbpby_enable_cnt--;
	if (usbpby_enable_cnt <= 0) {
		rv = clk_enable(sc->clk_pads);
		if (rv != 0) {
			device_printf(sc->dev,
			    "Cannot enable 'utmi-pads' clock\n");
			return (rv);
		}
		val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0);
		val |= UTMIP_OTGPD;
		val |= UTMIP_BIASPD;
		bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val);

		rv = clk_disable(sc->clk_pads);
		if (rv != 0) {
			device_printf(sc->dev,
			    "Cannot disable 'utmi-pads' clock\n");
			return (rv);
		}
	}
	return (0);
}

static void
lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
	struct lsi64854_softc *sc;

	sc = (struct lsi64854_softc *)arg;

	if (error != 0)
		return;
	if (nsegs != 1)
		panic("%s: cannot map %d segments\n", __func__, nsegs);

	bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
	    sc->sc_datain != 0 ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
	bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr);

	bus_write_4(sc->sc_res, L64854_REG_CNT, sc->sc_dmasize);
}

static void
hpet_disable(struct hpet_softc *sc)
{
	uint32_t val;

	val = bus_read_4(sc->mem_res, HPET_CONFIG);
	val &= ~HPET_CNF_ENABLE;
	bus_write_4(sc->mem_res, HPET_CONFIG, val);
}

static int
ata_kauai_dma_interrupt(struct ata_kauai_softc *sc)
{
	/* Clear the DMA interrupt bits */

	bus_write_4(sc->sc_memr, DMA_IRQ_REG, 0x80000000);

	return ata_interrupt(sc);
}

static void
bcm_dma_intr(void *arg)
{
	struct bcm_dma_softc *sc = bcm_dma_sc;
	struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg;
	uint32_t cs, debug;

	/* my interrupt? */
	cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch));

	if (!(cs & (CS_INT | CS_ERR)))
		return;

	/* running? */
	if (!(ch->flags & BCM_DMA_CH_USED)) {
		device_printf(sc->sc_dev,
		    "unused DMA intr CH=%d, CS=%x\n", ch->ch, cs);
		return;
	}

	if (cs & CS_ERR) {
		debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch));
		device_printf(sc->sc_dev, "DMA error %d on CH%d\n",
			debug & DEBUG_ERROR_MASK, ch->ch);
		bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch), 
		    debug & DEBUG_ERROR_MASK);
		bcm_dma_reset(sc->sc_dev, ch->ch);
	}

	if (cs & CS_INT) {
		/* acknowledge interrupt */
		bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch), 
		    CS_INT | CS_END);

		/* Prepare for possible access to len field */
		bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map,
		    BUS_DMASYNC_POSTWRITE);

		/* save callback function and argument */
		if (ch->intr_func)
			ch->intr_func(ch->ch, ch->intr_arg);
	}
}

void
terasic_mtl_reg_textcursor_set(struct terasic_mtl_softc *sc, uint8_t col,
    uint8_t row)
{
	uint32_t v;

	v = (col << TERASIC_MTL_TEXTCURSOR_COL_SHIFT) | row;
	v = htole32(v);
	bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR, v);
}