void
gdt_mpr_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx)
{
	GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", sc));

	if (ctx->istatus & 0x80) {		/* error flag */
		ctx->istatus &= ~0x80;
		ctx->cmd_status = bus_space_read_2(sc->sc_dpmemt,
		    sc->sc_dpmemh, GDT_MPR_STATUS);
		if (ctx->istatus == GDT_ASYNCINDEX) {
			ctx->service = bus_space_read_2(sc->sc_dpmemt,
			    sc->sc_dpmemh, GDT_MPR_SERVICE);
			ctx->info2 = bus_space_read_4(sc->sc_dpmemt,
			    sc->sc_dpmemh, GDT_MPR_INFO + sizeof (u_int32_t));
		}
	} else					/* no error */
		ctx->cmd_status = GDT_S_OK;

	ctx->info =
	    bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_INFO);

	if (gdt_polling)			/* init. -> more info */
		ctx->info2 = bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh,
		    GDT_MPR_INFO + sizeof (u_int32_t));
	bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
	bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA1, 0);
}

static int
fms_read_codec(void *addr, uint8_t reg, uint16_t *val)
{
	struct fms_softc *sc;
	int i;

	sc = addr;
	/* Poll until codec is ready */
	for (i = 0; i < TIMO && bus_space_read_2(sc->sc_iot, sc->sc_ioh,
		 FM_CODEC_CMD) & FM_CODEC_CMD_BUSY; i++)
		delay(1);
	if (i >= TIMO) {
		printf("fms: codec busy\n");
		return 1;
	}

	/* Write register index, read access */
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD,
			  reg | FM_CODEC_CMD_READ);

	/* Poll until we have valid data */
	for (i = 0; i < TIMO && !(bus_space_read_2(sc->sc_iot, sc->sc_ioh,
		 FM_CODEC_CMD) & FM_CODEC_CMD_VALID); i++)
		delay(1);
	if (i >= TIMO) {
		printf("fms: no data from codec\n");
		return 1;
	}

	/* Read data */
	*val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_DATA);
	return 0;
}

static void
flash_attach(device_t parent, device_t self, void *aux)
{
	char nbuf[32];
	struct flash_softc		*sc = device_private(self);
	struct arbus_attach_args	*aa = aux;
	int				i;
	bus_space_tag_t			iot = aa->aa_bst;
	bus_space_handle_t		ioh;
	uint16_t			venid, devid;

	if (bus_space_map(iot, aa->aa_addr, aa->aa_size, 0, &ioh)) {
		printf(": can't map i/o space\n");
                return;
  	}
	
	sc->sc_iot = iot;
	sc->sc_ioh = ioh;
	sc->sc_status = 0;

	/* issue JEDEC query */
	bus_space_write_2(aa->aa_bst, ioh, (0x5555 << 1), 0xAAAA);
	bus_space_write_2(aa->aa_bst, ioh, (0x2AAA << 1), 0x5555);
	bus_space_write_2(aa->aa_bst, ioh, (0x5555 << 1), 0x9090);

	delay(100);
	venid = bus_space_read_2(aa->aa_bst, ioh, 0);
	devid = bus_space_read_2(aa->aa_bst, ioh, 2);

	/* issue software exit */
	bus_space_write_2(aa->aa_bst, ioh, 0x0, 0xF0F0);

	for (i = 0; flash_ids[i].name != NULL; i++) {
		if ((venid == flash_ids[i].vendor_id) &&
		    (devid == flash_ids[i].device_id)) {
			break;
		}
	}

	KASSERT(flash_ids[i].name != NULL);
	printf(": %s", flash_ids[i].name);
	if (humanize_number(nbuf, sizeof(nbuf), flash_ids[i].flash_size, "B",
	    1024) > 0)
		printf(" (%s)", nbuf);

	/*
	 * determine size of the largest block
	 */
	sc->sc_size = flash_ids[i].flash_size;
	sc->sc_sector_size = flash_ids[i].sector_size;

	if ((sc->sc_buf = malloc(sc->sc_sector_size, M_DEVBUF, M_NOWAIT))
	    == NULL) {
		printf(": can't alloc buffer space\n");
		return;
	}

	printf("\n");
}

static void
aps_refresh_sensor_data(struct aps_softc *sc)
{
	int64_t temp;

	/* ask for new data */
	bus_space_write_1(sc->sc_iot, sc->sc_ioh, APS_INIT, 0x11);
	bus_space_write_1(sc->sc_iot, sc->sc_ioh, APS_CMD, 0x01);
	if (!aps_mem_read_1(sc->sc_iot, sc->sc_ioh, APS_ACCEL_STATE, 0x50))
		return;

	sc->aps_data.state =
	    bus_space_read_1(sc->sc_iot, sc->sc_ioh, APS_STATE);
	sc->aps_data.x_accel =
	    bus_space_read_2(sc->sc_iot, sc->sc_ioh, APS_XACCEL);
	sc->aps_data.y_accel =
	    bus_space_read_2(sc->sc_iot, sc->sc_ioh, APS_YACCEL);
	sc->aps_data.temp1 =
	    bus_space_read_1(sc->sc_iot, sc->sc_ioh, APS_TEMP);
	sc->aps_data.x_var =
	    bus_space_read_2(sc->sc_iot, sc->sc_ioh, APS_XVAR);
	sc->aps_data.y_var =
	    bus_space_read_2(sc->sc_iot, sc->sc_ioh, APS_YVAR);
	sc->aps_data.temp2 =
	    bus_space_read_1(sc->sc_iot, sc->sc_ioh, APS_TEMP2);
	sc->aps_data.input =
	    bus_space_read_1(sc->sc_iot, sc->sc_ioh, APS_INPUT);

	bus_space_write_1(sc->sc_iot, sc->sc_ioh, APS_INIT, 0x11);
	bus_space_write_1(sc->sc_iot, sc->sc_ioh, APS_CMD, 0x01);

	/* tell accelerometer we're done reading from it */
	bus_space_read_1(sc->sc_iot, sc->sc_ioh, APS_CMD);
	bus_space_read_1(sc->sc_iot, sc->sc_ioh, APS_ACCEL_STATE);

	sc->sc_sensor[APS_SENSOR_XACCEL].value_cur = sc->aps_data.x_accel;
	sc->sc_sensor[APS_SENSOR_YACCEL].value_cur = sc->aps_data.y_accel;

	/* convert to micro (mu) degrees */
	temp = sc->aps_data.temp1 * 1000000;	
	/* convert to kelvin */
	temp += 273150000; 
	sc->sc_sensor[APS_SENSOR_TEMP1].value_cur = temp;

	/* convert to micro (mu) degrees */
	temp = sc->aps_data.temp2 * 1000000;	
	/* convert to kelvin */
	temp += 273150000; 
	sc->sc_sensor[APS_SENSOR_TEMP2].value_cur = temp;

	sc->sc_sensor[APS_SENSOR_XVAR].value_cur = sc->aps_data.x_var;
	sc->sc_sensor[APS_SENSOR_YVAR].value_cur = sc->aps_data.y_var;
	sc->sc_sensor[APS_SENSOR_KBACT].value_cur =
	    (sc->aps_data.input &  APS_INPUT_KB) ? 1 : 0;
	sc->sc_sensor[APS_SENSOR_MSACT].value_cur =
	    (sc->aps_data.input & APS_INPUT_MS) ? 1 : 0;
	sc->sc_sensor[APS_SENSOR_LIDOPEN].value_cur =
	    (sc->aps_data.input & APS_INPUT_LIDOPEN) ? 1 : 0;
}

static int
dl_match (struct device *parent, struct cfdata *cf, void *aux)
{
	struct uba_attach_args *ua = aux;

#ifdef DL_DEBUG
	printf("Probing for dl at %lo ... ", (long)ua->ua_iaddr);
#endif

	bus_space_write_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR, DL_XCSR_TXIE);
	if (bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR) !=
	    (DL_XCSR_TXIE | DL_XCSR_TX_READY)) {
#ifdef DL_DEBUG
		printf("failed (step 1; XCSR = %.4b)\n",
		    bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR),
		    DL_XCSR_BITS);
#endif
		return 0;
	}

	/*
	 * We have to force an interrupt so the uba driver can work
	 * out where we are.  Unfortunately, the only way to make a
	 * DL11 interrupt is to get it to send or receive a
	 * character.  We'll send a NUL and hope it doesn't hurt
	 * anything.
	 */

	bus_space_write_1(ua->ua_iot, ua->ua_ioh, DL_UBA_XBUFL, '\0');
#if 0 /* This test seems to fail 2/3 of the time :-( */
	if (dladdr->dl_xcsr != (DL_XCSR_TXIE)) {
#ifdef DL_DEBUG
		printf("failed (step 2; XCSR = %.4b)\n", dladdr->dl_xcsr,
		    DL_XCSR_BITS);
#endif
		return 0;
	}
#endif
	DELAY(100000); /* delay 1/10 s for character to transmit */
	if (bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR) !=
	    (DL_XCSR_TXIE | DL_XCSR_TX_READY)) {
#ifdef DL_DEBUG
		printf("failed (step 3; XCSR = %.4b)\n",
		    bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR),
		    DL_XCSR_BITS);
#endif
		return 0;
	}


	/* What else do I need to do? */

	return 1;

}

void
geodesc_attach(struct device *parent, struct device *self, void *aux)
{
	struct geodesc_softc *sc = (void *) self;
	struct pci_attach_args *pa = aux;
	uint16_t cnfg, cba;
	uint8_t sts, rev, iid;
	pcireg_t reg;
	extern void (*cpuresetfn)(void);

	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SC1100_F5_SCRATCHPAD);
	sc->sc_iot = pa->pa_iot;
	if (reg == 0 ||
	    bus_space_map(sc->sc_iot, reg, 64, 0, &sc->sc_ioh)) {
		printf(": unable to map registers at 0x%x\n", reg);
		return;
	}
	cba = bus_space_read_2(sc->sc_iot, sc->sc_ioh, GCB_CBA);
	if (cba != reg) {
		printf(": cba mismatch: cba 0x%x != reg 0x%x\n", cba, reg);
		bus_space_unmap(sc->sc_iot, sc->sc_ioh, 64);
		return;
	}
	sts = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GCB_WDSTS);
	cnfg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, GCB_WDCNFG);
	iid = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GCB_IID);
	rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GCB_REV);

	printf(": iid %d revision %d wdstatus %b\n", iid, rev, sts, WDSTSBITS);

#ifndef SMALL_KERNEL
	/* setup and register watchdog */
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, GCB_WDTO, 0);
	sts |= WDOVF_CLEAR;
	bus_space_write_1(sc->sc_iot, sc->sc_ioh, GCB_WDSTS, sts);
	cnfg &= ~WDCNFG_MASK;
	cnfg |= WDTYPE1_RESET|WDPRES_DIV_512;
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, GCB_WDCNFG, cnfg);

	wdog_register(sc, geodesc_wdogctl_cb);
#endif /* SMALL_KERNEL */

#ifdef __HAVE_TIMECOUNTER
	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GCB_TSCNFG, TSC_ENABLE);
	/* Hook into the kern_tc */
	geodesc_timecounter.tc_priv = sc;
	tc_init(&geodesc_timecounter);
#endif /* __HAVE_TIMECOUNTER */

	/* We have a special way to reset the CPU on the SC1100 */
	cpuresetfn = sc1100_sysreset;
}

int
imxuart_intr(void *arg)
{
	struct imxuart_softc *sc = arg;
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	struct tty *tp = sc->sc_tty;
	u_int16_t sr1;
	u_int16_t *p;
	u_int16_t c;

	sr1 = bus_space_read_2(iot, ioh, IMXUART_USR1);
	if (ISSET(sr1, IMXUART_SR1_TRDY) && ISSET(tp->t_state, TS_BUSY)) {
		CLR(tp->t_state, TS_BUSY | TS_FLUSH);
		if (sc->sc_halt > 0)
			wakeup(&tp->t_outq);
		(*linesw[tp->t_line].l_start)(tp);
	}

	if (sc->sc_tty == NULL)
		return(0);

	if(!ISSET(bus_space_read_2(iot, ioh, IMXUART_USR2), IMXUART_SR2_RDR))
		return 0;

	p = sc->sc_ibufp;

	while(ISSET(bus_space_read_2(iot, ioh, IMXUART_USR2), IMXUART_SR2_RDR)) {
		c = bus_space_read_1(iot, ioh, IMXUART_URXD);
		if (p >= sc->sc_ibufend) {
			sc->sc_floods++;
			if (sc->sc_errors++ == 0)
				timeout_add(&sc->sc_diag_tmo, 60 * hz);
		} else {
			*p++ = c;
			if (p == sc->sc_ibufhigh &&
			    ISSET(tp->t_cflag, CRTSCTS)) {
				/* XXX */
				CLR(sc->sc_ucr3, IMXUART_CR3_DSR);
				bus_space_write_2(iot, ioh, IMXUART_UCR3,
				    sc->sc_ucr3);
			}

		}
		/* XXX - msr stuff ? */
	}
	sc->sc_ibufp = p;

	softintr_schedule(sc->sc_si);

	return 1;
}

int
sm_obio_match(device_t parent, cfdata_t match, void *aux)
{
	struct obio_attach_args *oba = aux;
	bus_space_tag_t iot = &smobio8_bs_tag;
	bus_space_handle_t ioh;
	uint16_t tmp;
	int rv = 0;
	extern const char *smc91cxx_idstrs[];


	/* Map i/o space. */
	if (bus_space_map(iot, oba->oba_addr, SMC_IOSIZE, 0, &ioh))
		return (0);


	/* Check that high byte of BANK_SELECT is what we expect. */
	tmp = bus_space_read_2(iot, ioh, BANK_SELECT_REG_W);
	if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE)
		goto out;

	/*
	 * Switch to bank 0 and perform the test again.
	 * XXX INVASIVE!
	 */
	bus_space_write_1(iot, ioh, BANK_SELECT_REG_W, 0);
	tmp = bus_space_read_2(iot, ioh, BANK_SELECT_REG_W);
	if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE)
		goto out;

	/*
	 * Check for a recognized chip id.
	 * XXX INVASIVE!
	 */
	bus_space_write_1(iot, ioh, BANK_SELECT_REG_W, 3);
	tmp = bus_space_read_2(iot, ioh, REVISION_REG_W);
	if (smc91cxx_idstrs[RR_ID(tmp)] == NULL)
		goto out;

	/*
	 * Assume we have an SMC91Cxx.
	 */

	rv = 1;

 out:
	bus_space_unmap(iot, ioh, SMC_IOSIZE);
	if (!rv) {
		printf("on-board SMC probe failed\n");
	}
	return (rv);
}

int
amdpm_intr(void *arg)
{
	struct amdpm_softc *sc = arg;
	u_int16_t st, data;
	u_int8_t *b;
	size_t len;

	/* Read status */
	st = bus_space_read_2(sc->sc_iot, sc->sc_i2c_ioh, AMDPM_SMBSTAT);
	if ((st & AMDPM_SMBSTAT_HBSY) != 0 || (st & (AMDPM_SMBSTAT_ABRT |
	    AMDPM_SMBSTAT_COL | AMDPM_SMBSTAT_PRERR | AMDPM_SMBSTAT_CYC |
	    AMDPM_SMBSTAT_TO | AMDPM_SMBSTAT_SNP | AMDPM_SMBSTAT_SLV |
	    AMDPM_SMBSTAT_SMBA)) == 0)
		/* Interrupt was not for us */
		return (0);

	DPRINTF("%s: intr: st 0x%b\n", sc->sc_dev.dv_xname, st,
	    AMDPM_SMBSTAT_BITS);

	/* Clear status bits */
	bus_space_write_2(sc->sc_iot, sc->sc_i2c_ioh, AMDPM_SMBSTAT, st);

	/* Check for errors */
	if (st & (AMDPM_SMBSTAT_COL | AMDPM_SMBSTAT_PRERR |
	    AMDPM_SMBSTAT_TO)) {
		sc->sc_i2c_xfer.error = 1;
		goto done;
	}

	if (st & AMDPM_SMBSTAT_CYC) {
		if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op))
			goto done;

		/* Read data */
		b = sc->sc_i2c_xfer.buf;
		len = sc->sc_i2c_xfer.len;
		if (len > 0) {
			data = bus_space_read_2(sc->sc_iot, sc->sc_i2c_ioh,
			    AMDPM_SMBDATA);
			b[0] = data & 0xff;
		}
		if (len > 1)
			b[1] = (data >> 8) & 0xff;
	}

done:
	if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0)
		wakeup(sc);
	return (1);
}

u_int
elansc_tc_read(struct timecounter *tc)
{
	struct elansc_softc *sc = tc->tc_priv;
	u_int32_t m1, m2, l;

	do {
		m1 = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT);
		l = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR2CNT);
		m2 = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT);
	} while (m1 != m2);

	return ((m1 << 16) | l);
}

static int
geode_attach(device_t self)
{
	u_int32_t	reg;
	u_int16_t	cnfg, cba;
	u_int8_t	sts, rev, iid;

	/*
	 * The address of the CBA is written to this register
	 * by the bios, see p161 in data sheet.
	 */
	reg = pci_read_config(self, SC1100_F5_SCRATCHPAD, 4);
	if (reg == 0)
		return ENODEV;

	/* bus_space_map(sc->sc_iot, reg, 64, 0, &sc->sc_ioh)) */
	geode_sc.sc_iot = I386_BUS_SPACE_IO;
	geode_sc.sc_ioh = reg;

	cba = bus_space_read_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_CBA);
	if (cba != reg) {
		kprintf("Geode LX: cba mismatch: cba 0x%x != reg 0x%x\n", cba, reg);
		return ENODEV;
	}

	/* outl(cba + 0x0d, 2); ??? */
	sts = bus_space_read_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDSTS);
	cnfg = bus_space_read_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDCNFG);
	iid = bus_space_read_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_IID);
	rev = bus_space_read_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_REV);
#define WDSTSBITS "\20\x04WDRST\x03WDSMI\x02WDINT\x01WDOVF"
	kprintf("Geode LX: iid %d revision %d wdstatus %b\n", iid, rev, sts, WDSTSBITS);

	/* enable timer */
	bus_space_write_4(geode_sc.sc_iot, geode_sc.sc_iot, GCB_TSCNFG, TSC_ENABLE);
	cputimer_register(&geode_timer);
	cputimer_select(&geode_timer, 0);

	/* enable watchdog and configure */
	bus_space_write_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDTO, 0);
	sts |= WDOVF_CLEAR;
	bus_space_write_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDSTS, sts);
	cnfg &= ~WDCNFG_MASK;
	cnfg |= WDTYPE1_RESET | WDPRES_DIV_512;
	bus_space_write_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDCNFG, cnfg);
	wdog_register(&geode_wdog);

	return 0;
}

static void
geode_wdog_disable(struct geode_wdog_softc *sc)
{
	uint16_t wdcnfg;

	/* cancel any pending countdown */
	sc->sc_countdown = 0;
	bus_space_write_2(sc->sc_gcb_dev->sc_iot, sc->sc_gcb_dev->sc_ioh,
	    SC1100_GCB_WDTO, 0);
	/* power-down clock */
	wdcnfg = bus_space_read_2(sc->sc_gcb_dev->sc_iot,
	    sc->sc_gcb_dev->sc_ioh, SC1100_GCB_WDCNFG);

	GEODE_DPRINTF(("%s: wdcnfg %#04" PRIx16 " -> ", __func__, wdcnfg));

	wdcnfg |= SC1100_WDCNFG_WD32KPD;
	wdcnfg &= ~(SC1100_WDCNFG_WDTYPE2_MASK | SC1100_WDCNFG_WDTYPE1_MASK);
	/* This no-op is for the reader's benefit. */
        wdcnfg |= SC1100_WDCNFG_WDTYPE1_NOACTION |
                  SC1100_WDCNFG_WDTYPE2_NOACTION;
	bus_space_write_2(sc->sc_gcb_dev->sc_iot, sc->sc_gcb_dev->sc_ioh,
	    SC1100_GCB_WDCNFG, wdcnfg);

	GEODE_DPRINTF(("%#04" PRIx16 "\n", wdcnfg));
}

int
bppintr(void *arg)
{
	struct bpp_softc *sc = arg;
	struct lsi64854_softc *lsi = &sc->sc_lsi64854;
	uint16_t irq;

	/* First handle any possible DMA interrupts */
	if (lsi64854_pp_intr((void *)lsi) == -1)
		sc->sc_error = 1;

	irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR);
	/* Ack all interrupts */
	bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR,
	    irq | BPP_ALLIRQ);

	DPRINTF(("%s: %x\n", __func__, irq));
	/* Did our device interrupt? */
	if ((irq & BPP_ALLIRQ) == 0)
		return 0;

	if ((sc->sc_flags & BPP_LOCKED) != 0)
		wakeup(sc);
	else if ((sc->sc_flags & BPP_WANT) != 0) {
		sc->sc_flags &= ~BPP_WANT;
		wakeup(sc->sc_buf);
	} else {
		selnotify(&sc->sc_wsel, 0, 0);
		if (sc->sc_asyncproc != NULL)
			softint_schedule(sc->sc_sih);
	}
	return 1;
}

static uint32_t
pcib_mbus_hw_cfgread(struct pcib_mbus_softc *sc, u_int bus, u_int slot,
    u_int func, u_int reg, int bytes)
{
	uint32_t addr, data, ca, cd;

	ca = (sc->sc_info->op_type != MV_TYPE_PCI) ?
	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
	cd = (sc->sc_info->op_type != MV_TYPE_PCI) ?
	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);

	mtx_lock_spin(&pcicfg_mtx);
	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);

	data = ~0;
	switch (bytes) {
	case 1:
		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
		    cd + (reg & 3));
		break;
	case 2:
		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
		    cd + (reg & 2)));
		break;
	case 4:
		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
		    cd));
		break;
	}
	mtx_unlock_spin(&pcicfg_mtx);
	return (data);
}

static uint8_t
cfi_read_qry(struct cfi * const cfi, bus_size_t off)
{
	const bus_space_tag_t bst = cfi->cfi_bst;
	bus_space_handle_t bsh = cfi->cfi_bsh;
	uint8_t data;

	off <<= cfi->cfi_portwidth;

	switch (cfi->cfi_portwidth) {
	case 0:
		data = bus_space_read_1(bst, bsh, off);
		break;
	case 1:
		data = bus_space_read_2(bst, bsh, off);
		break;
	case 2:
		data = bus_space_read_4(bst, bsh, off);
		break;
	case 3:
		data = bus_space_read_8(bst, bsh, off);
		break;
	default:
		data = ~0;
		break;
	}
	return data;
}

static int
gtp_state(bus_space_tag_t iot, bus_space_handle_t ioh)
{
	int ret;

	bus_space_write_2(iot, ioh, 0,
	    GTP_DATA_ON | GTP_WREN_OFF | GTP_CLCK_OFF);
	ret  = bus_space_read_2(iot, ioh, 0) &
	    GEMTEK_PCI_STEREO?  0 : RADIO_INFO_STEREO;
	bus_space_write_2(iot, ioh, 0,
	    GTP_DATA_ON | GTP_WREN_OFF | GTP_CLCK_ON);
	ret |= bus_space_read_2(iot, ioh, 0) &
	    GEMTEK_PCI_SIGNAL?  0 : RADIO_INFO_SIGNAL;

	return ret;
}

static uint16_t
amdpm_smbus_get_gsr(struct amdpm_softc *sc)
{
	int off = (sc->sc_nforce ? 0xe0 : 0);
        return bus_space_read_2(sc->sc_iot, sc->sc_ioh,
	    AMDPM_8111_SMBUS_STAT - off);
}

int
bppintr(void *arg)
{
	struct bpp_softc *sc = arg;
	struct lsi64854_softc *lsi = &sc->sc_lsi64854;
	u_int16_t irq;

	/* First handle any possible DMA interrupts */
	if (DMA_INTR(lsi) == -1)
		sc->sc_error = 1;

	irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR);
	/* Ack all interrupts */
	bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR,
			  irq | BPP_ALLIRQ);

	DPRINTF(("bpp_intr: %x\n", irq));
	/* Did our device interrupt? */
	if ((irq & BPP_ALLIRQ) == 0)
		return (0);

	if ((sc->sc_flags & BPP_LOCKED) != 0)
		wakeup(sc);
	else if ((sc->sc_flags & BPP_WANT) != 0) {
		sc->sc_flags &= ~BPP_WANT;
		wakeup(sc->sc_buf);
	}
	return (1);
}

void
snc_nec16_dump_reg(bus_space_tag_t iot, bus_space_handle_t ioh)
{
	u_int8_t n;
	u_int16_t val;

	printf("SONIC registers (word):");
	for (n = 0; n < SNC_NREGS; n++) {
		/* select required SONIC register */
		bus_space_write_1(iot, ioh, SNEC_ADDR, n);
		DELAY(10);
		val = bus_space_read_2(iot, ioh, SNEC_CTRL);
		if ((n % 0x10) == 0)
			printf("\n%04x ", val);
		else
			printf("%04x ", val);
	}
	printf("\n");

	printf("NEC/SONIC registers (byte):\n");
	for (n = SNECR_MEMBS; n <= SNECR_IDENT; n += 2) {
		/* select required SONIC register */
		bus_space_write_1(iot, ioh, SNEC_ADDR, n);
		DELAY(10);
		val = (u_int16_t) bus_space_read_1(iot, ioh, SNEC_CTRLB);
		printf("%04x ", val);
	}
	printf("\n");
}

static int
agg_rdcodec(kobj_t obj, void *sc, int regno)
{
	struct agg_info *ess = sc;
	unsigned t;

	/* We have to wait for a SAFE time to write addr/data */
	for (t = 0; t < 20; t++) {
		if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
		    & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
			break;
		DELAY(2);	/* 20.8us / 13 */
	}
	if (t == 20)
		device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");

	bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
	    CODEC_CMD_READ | regno);
	DELAY(21);	/* AC97 cycle = 20.8usec */

	/* Wait for data retrieve */
	for (t = 0; t < 20; t++) {
		if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
		    & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
			break;
		DELAY(2);	/* 20.8us / 13 */
	}
	if (t == 20)
		/* Timed out, but perform dummy read. */
		device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");

	return bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
}