static void bootblock_southbridge_init(void)
{
	pci_devfn_t dev;
	/* don't walk other busses, HT is not enabled */

	/* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */
	/* ROM decode last 4MB FFC00000 - FFFFFFFF on VT8237R */

	/* Power management controller */
	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
		    PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);

	if (dev != PCI_DEV_INVALID)
		goto found;

	/* Power management controller */
	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
		PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);

	if (dev != PCI_DEV_INVALID)
		goto found;

	/* Power management controller */
	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
		PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);

	if (dev == PCI_DEV_INVALID)
		return;

found:
	pci_write_config8(dev, 0x41, 0x7f);
}

static void bcm5785_enable_wdt_port_cf9(void)
{
	pci_devfn_t dev;
	uint32_t dword;
	uint32_t dword_old;

	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);

	dword_old = pci_read_config32(dev, 0x4c);
	dword = dword_old | (1<<4); //enable Timer Func
	if (dword != dword_old ) {
		pci_write_config32(dev, 0x4c, dword);
	}

	dword_old = pci_read_config32(dev, 0x6c);
	dword = dword_old | (1<<9); //unhide Timer Func in pci space
	if (dword != dword_old ) {
		pci_write_config32(dev, 0x6c, dword);
	}

	dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);

	/* enable cf9 */
	pci_write_config8(dev, 0x40, (1<<2));
}

static void enable_smbus(void)
{
	device_t dev;
	unsigned char c;
	/* Power management controller */
	dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);

	if (dev == PCI_DEV_INVALID) {
		die("SMBUS controller not found\n");
	}
	// set IO base address to SMBUS_IO_BASE
	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);

	// Enable SMBus
	c = pci_read_config8(dev, 0xd2);
	c |= 5;
	pci_write_config8(dev, 0xd2, c);

	/* make it work for I/O ...
	 */
	dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
	c = pci_read_config8(dev, 4);
	c |= 1;
	pci_write_config8(dev, 4, c);
	print_debug_hex8(c);
	print_debug(" is the comm register\n");

	print_debug("SMBus controller enabled\n");
}

static void enable_mainboard_devices(void)
{
	device_t dev;
	/* dev 0 for southbridge */

	dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);

	if (dev == PCI_DEV_INVALID)
		die("Southbridge not found!!!\n");

	pci_write_config8(dev, 0x50, 7);
	pci_write_config8(dev, 0x51, 0xff);
#if 0
	// This early setup switches IDE into compatibility mode before PCI gets
	// a chance to assign I/Os
	//   movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
	//   movb    $0x09, %dl
	//   movb    $0x00, %dl
	//   PCI_WRITE_CONFIG_BYTE
	//
#endif
	/* we do this here as in V2, we can not yet do raw operations
	 * to pci!
	 */
	/* changed this to work correctly on later revisions of LB.
	* The original dev += 0x100; stopped working. It also appears
	* that if this is not set here, but in ide_init() only, the IDE
	* does not work at all. I assume it needs to be set before something else,
	* possibly before enabling the IDE peripheral, or it is a timing issue.
	* Ben Hewson 29 Apr 2007.
	*/

	dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0);
	pci_write_config8(dev, 0x42, 0);
}

static void enable_mainboard_devices(void)
{
	device_t dev;

	dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
	if (dev == PCI_DEV_INVALID) {
		die("LPC bridge not found!!!\n");
	}
	// Disable GP3
	pci_write_config8(dev, 0x98, 0x00);

	// Disable mc97
	pci_write_config8(dev, 0x50, 0x80);

	// Disable internal KBC Configuration
	pci_write_config8(dev, 0x51, 0x2d);
	pci_write_config8(dev, 0x58, 0x42);
	pci_write_config8(dev, 0x59, 0x80);
	pci_write_config8(dev, 0x5b, 0x01);

	// Enable P2P Bridge Header for External PCI BUS.
	dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
	if (dev == PCI_DEV_INVALID) {
		die("P2P bridge not found!!!\n");
	}
	pci_write_config8(dev, 0x4f, 0x41);

	// Switch SATA to non-RAID mode
	dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
	if (dev != PCI_DEV_INVALID) {
		pci_write_config16(dev, 0xBA, 0x5324);
	}
}

static void mcp55_enable_rom(void)
{
	u8 byte;
	u16 word;
	device_t addr;

	/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
#if 0
	/* Default MCP55 LPC single */
	addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
#else
//	addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
	addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0);
#endif

	/* Set the 15MB enable bits. */
	byte = pci_read_config8(addr, 0x88);
	byte |= 0xff; /* 256K */
	pci_write_config8(addr, 0x88, byte);
	byte = pci_read_config8(addr, 0x8c);
	byte |= 0xff; /* 1M */
	pci_write_config8(addr, 0x8c, byte);
	word = pci_read_config16(addr, 0x90);
	word |= 0x7fff; /* 15M */
	pci_write_config16(addr, 0x90, word);
}

static void enable_mainboard_devices(void)
{
	device_t dev;

	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
				PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
	if (dev == PCI_DEV_INVALID)
		die("Southbridge not found!!!\n");

	/* bit=0 means enable function (per CX700 datasheet)
	 *   5 16.1 USB 2
	 *   4 16.0 USB 1
	 *   3 15.0 SATA and PATA
	 *   2 16.2 USB 3
	 *   1 16.4 USB EHCI
	 */
	pci_write_config8(dev, 0x50, 0x80);

	/* bit=1 means enable internal function (per CX700 datasheet)
	 *   3 Internal RTC
	 *   2 Internal PS2 Mouse
	 *   1 Internal KBC Configuration
	 *   0 Internal Keyboard Controller
	 */
	pci_write_config8(dev, 0x51, 0x1d);
}

static void mch_reset(void)
{
        device_t dev;
        unsigned long value, base;
        dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0);
        if (dev != PCI_DEV_INVALID) {
                /* I/O space is always enables */

                /* Set gpio base */
                pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
                base = ICH5_GPIOBASE;

                /* Enable GPIO Bar */
                value = pci_read_config32(dev, 0x5c);
                value |= 0x10;
                pci_write_config32(dev, 0x5c, value);

		/* Set GPIO 19 mux to IO usage */
		value = inl(base);
		value |= (1 <<19);
		outl(value, base);

                /* Pull GPIO 19 low */
                value = inl(base + 0x0c);
                value &= ~(1 << 19);
                outl(value, base + 0x0c);
        }
        return;
}

static void enable_mainboard_devices(void)
{
	device_t dev;
	u8 reg;

	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
				PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
	if (dev == PCI_DEV_INVALID)
		die("Southbridge not found!!!\n");

	/* bit=0 means enable function (per VT8237R datasheet)
	 *   7 17.6 MC97
	 *   6 17.5 AC97
	 *   5 16.1 USB 2
	 *   4 16.0 USB 1
	 *   3 15.0 SATA and PATA
	 *   2 16.2 USB 3
	 *   1 16.4 USB EHCI
	 */
	pci_write_config8(dev, 0x50, 0xC0);

	/*bit=0 means enable internal function (per VT8237R datasheet)
	 *   7 USB Device Mode
	 *bit=1 means enable internal function (per VT8237R datasheet)
	 *   6 Reserved
	 *   5 LAN Controller Clock Gating
	 *   4 LAN Controller
	 *   3 Internal RTC
	 *   2 Internal PS2 Mouse
	 *   1 Internal KBC Configuration
	 *   0 Internal Keyboard Controller
	 */
	pci_write_config8(dev, 0x51, 0x9d);
}

static void disable_esb6300_watchdog(void)
{
	/* FIXME move me somewhere more appropriate */
	device_t dev;
	unsigned long value, base;
	dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
	if (dev == PCI_DEV_INVALID) {
		die("Missing 6300ESB?");
	}
	/* Enable I/O space */
	value = pci_read_config16(dev, 0x04);
	value |= (1 << 10);
	pci_write_config16(dev, 0x04, value);

	/* Set and enable acpibase */
	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
	pci_write_config8(dev, 0x44, 0x10);
	base = ICH5_WDBASE + 0x60;

	/* Set bit 11 in TCO1_CNT */
	value = inw(base + 0x08);
	value |= 1 << 11;
	outw(value, base + 0x08);

	/* Clear TCO timeout status */
	outw(0x0008, base + 0x04);
	outw(0x0002, base + 0x06);
}

/*
 * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
 *
 * Hardware should enable LPC ROM by pin straps. This function does not
 * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
 *
 * The SB600 power-on default is to map 256K ROM space.
 *
 * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15.
 */
static void sb600_enable_rom(void)
{
	u8 reg8;
	pci_devfn_t dev;

	dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
			PCI_DEVICE_ID_ATI_SB600_LPC), 0);

	/* Decode variable LPC ROM address ranges 1 and 2. */
	reg8 = pci_io_read_config8(dev, 0x48);
	reg8 |= (1 << 3) | (1 << 4);
	pci_io_write_config8(dev, 0x48, reg8);

	/* LPC ROM address range 1: */
	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
	pci_io_write_config16(dev, 0x68, 0x000e);
	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
	pci_io_write_config16(dev, 0x6a, 0x000f);

	/* LPC ROM address range 2: */
	/*
	 * Enable LPC ROM range start at:
	 * 0xfff8(0000): 512KB
	 * 0xfff0(0000): 1MB
	 * 0xffe0(0000): 2MB
	 * 0xffc0(0000): 4MB
	 */
	pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* 4 MB */
	/* Enable LPC ROM range end at 0xffff(ffff). */
	pci_io_write_config16(dev, 0x6e, 0xffff);
}

void enable_smbus(void)
{
	pci_devfn_t dev;

	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0);

	if (dev == PCI_DEV_INVALID) {
		/* This won't display text if enable_smbus() is before serial init */
		die("Power Managment Controller not found\n");
	}

	/* Set clock source */
	pci_write_config8(dev, 0x94, 0x20);

	/* Write SMBus IO base to 0xd0, and enable SMBus */
	pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);

	/* Set to Award value */
	pci_write_config8(dev, 0xd2, 0x05);

	/* Make it work for I/O ... */
	pci_write_config16(dev, 0x04, 0x0003);

	smbus_reset();
	/* clear host data port */
	outb(0x00, SMBHSTDAT0);
	SMBUS_DELAY();
	smbus_wait_until_ready();
}

/* RPR 2.28: Get SB ASIC Revision. */
static u8 set_sb700_revision(void)
{
	pci_devfn_t dev;
	u8 rev_id, enable_14Mhz, byte;
	u8 rev = 0;

	/* if (rev != 0) return rev; */

	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);

	if (dev == PCI_DEV_INVALID) {
		die("SMBUS controller not found\n");
		/* NOT REACHED */
	}
	rev_id =  pci_read_config8(dev, 0x08);

	if (rev_id == 0x39) {
		enable_14Mhz = (pmio_read(0x53) >> 6) & 1;
		if (enable_14Mhz == 0x0)
			rev = 0x11;	/* A11 */
		else if (enable_14Mhz == 0x1) {
			/* This happens, if does, only once. So later if we need to get
			 * the revision ID, we don't have to make such a big function.
			 * We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */
			rev = 0x12;
			byte = pci_read_config8(dev, 0x40);
			byte |= 1 << 0;
			pci_write_config8(dev, 0x40, byte);

			pci_write_config8(dev, 0x08, 0x3A); /* Change 0x39 to 0x3A. */

			byte &= ~(1 << 0);
			pci_write_config8(dev, 0x40, byte);
		}
	} else if (rev_id == 0x3A) { /* A12 will be 0x3A after BIOS is initialized */

static void enable_mainboard_devices(void)
{
	device_t dev;

	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
				       PCI_DEVICE_ID_VIA_8235), 0);

	if (dev == PCI_DEV_INVALID) {
		die("Southbridge not found!!!\n");
	}
	pci_write_config8(dev, 0x50, 0x80);
	pci_write_config8(dev, 0x51, 0x1f);
#if 0
	// This early setup switches IDE into compatibility mode before PCI gets
	// a chance to assign I/Os
	// movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
	// //      movb    $0x09, %dl
	// movb    $0x00, %dl
	// PCI_WRITE_CONFIG_BYTE
#endif
	/* we do this here as in V2, we can not yet do raw operations
	 * to pci!
	 */
        dev += 0x100; /* ICKY */

	pci_write_config8(dev, 0x04, 7);
	pci_write_config8(dev, 0x40, 3);
	pci_write_config8(dev, 0x42, 0);
	pci_write_config8(dev, 0x3c, 0xe);
	pci_write_config8(dev, 0x3d, 0);
}

static void bcm5785_enable_msg(void)
{
	pci_devfn_t dev;
	uint32_t dword;
	uint32_t dword_old;
	uint8_t byte;

	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);

	byte = pci_read_config8(dev, 0x42);
	byte = (1<<1); //enable a20
	pci_write_config8(dev, 0x42, byte);

	dword_old = pci_read_config32(dev, 0x6c);
	// bit 5: enable A20 Message
	// bit 4: enable interrupt messages
	// bit 3: enable reset init message
	// bit 2: enable keyboard init message
	// bit 1: enable upsteam messages
	// bit 0: enable shutdowm message to init generation
	dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
	if (dword != dword_old ) {
		pci_write_config32(dev, 0x6c, dword);
	}
}

/* what is its usage? */
static u32 get_sbdn(u32 bus)
{
	device_t dev;

	/* Find the device. */
	dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
	return (dev >> 15) & 0x1f;
}

unsigned int get_sbdn(unsigned bus)
{
	device_t dev;

	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
					PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
	return (dev >> 15) & 0x1f;
}

/**
 * @brief Get SouthBridge device number
 * @param[in] bus target bus number
 * @return southbridge device number
 */
unsigned int get_sbdn(unsigned bus)
{
	pci_devfn_t dev;

	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
					PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
	return (dev >> 15) & 0x1f;
}

void sb600_lpc_port80(void)
{
	u8 byte;
	device_t dev;
	u32 reg32;

	/* Enable LPC controller */
	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
	reg32 = pci_read_config32(dev, 0x64);
	reg32 |= 0x00100000;	/* lpcEnable */
	pci_write_config32(dev, 0x64, reg32);

	/* Enable port 80 LPC decode in pci function 3 configuration space. */
	dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);
	byte = pci_read_config8(dev, 0x4a);
	byte |= 1 << 5;		/* enable port 80 */
	pci_write_config8(dev, 0x4a, byte);
}

void sb600_pci_port80(void)
{
	u8 byte;
	device_t dev;

	/* P2P Bridge */
	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);

	/* Chip Control: Enable subtractive decoding */
	byte = pci_read_config8(dev, 0x40);
	byte |= 1 << 5;
	pci_write_config8(dev, 0x40, byte);

	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
	byte = pci_read_config8(dev, 0x4B);
	byte |= 1 << 7;
	pci_write_config8(dev, 0x4B, byte);

	/* The same IO Base and IO Limit here is meaningful because we set the
	 * bridge to be subtractive. During early setup stage, we have to make
	 * sure that data can go through port 0x80.
	 */
	/* IO Base: 0xf000 */
	byte = pci_read_config8(dev, 0x1C);
	byte |= 0xF << 4;
	pci_write_config8(dev, 0x1C, byte);

	/* IO Limit: 0xf000 */
	byte = pci_read_config8(dev, 0x1D);
	byte |= 0xF << 4;
	pci_write_config8(dev, 0x1D, byte);

	/* PCI Command: Enable IO response */
	byte = pci_read_config8(dev, 0x04);
	byte |= 1 << 0;
	pci_write_config8(dev, 0x04, byte);

	/* LPC controller */
	dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);

	byte = pci_read_config8(dev, 0x4A);
	byte &= ~(1 << 5);	/* disable lpc port 80 */
	pci_write_config8(dev, 0x4A, byte);
}