void pci_init_board(void)
{
    struct pci_controller* hose = (struct pci_controller *)&local_hose;
    u16 reg16;

    hose->first_busno = 0;
    hose->last_busno = 0xff;

    pci_set_region(hose->regions + 0,
	CONFIG_SYS_PCI_MEMORY_BUS,
	CONFIG_SYS_PCI_MEMORY_PHYS,
	CONFIG_SYS_PCI_MEMORY_SIZE,
	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

    /* PCI memory space */
    pci_set_region(hose->regions + 1,
	CONFIG_SYS_PCI_MEM_BUS,
	CONFIG_SYS_PCI_MEM_PHYS,
	CONFIG_SYS_PCI_MEM_SIZE,
	PCI_REGION_MEM);

    /* ISA/PCI memory space */
    pci_set_region(hose->regions + 2,
	CONFIG_SYS_ISA_MEM_BUS,
	CONFIG_SYS_ISA_MEM_PHYS,
	CONFIG_SYS_ISA_MEM_SIZE,
	PCI_REGION_MEM);

    /* PCI I/O space */
    pci_set_region(hose->regions + 3,
	CONFIG_SYS_PCI_IO_BUS,
	CONFIG_SYS_PCI_IO_PHYS,
	CONFIG_SYS_PCI_IO_SIZE,
	PCI_REGION_IO);

    /* ISA/PCI I/O space */
    pci_set_region(hose->regions + 4,
	CONFIG_SYS_ISA_IO_BUS,
	CONFIG_SYS_ISA_IO_PHYS,
	CONFIG_SYS_ISA_IO_SIZE,
	PCI_REGION_IO);

    hose->region_count = 5;

    pci_setup_indirect(hose,
	MPC106_REG_ADDR,
	MPC106_REG_DATA);

    pci_register_hose(hose);

    hose->last_busno = pci_hose_scan(hose);

    /* Initialises the MPC10x PCI Configuration regs. */
    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);

    /* Clear non-reserved bits in status register */
    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
}

void pci_init_board(void)
{
	struct pci_controller *hose;

	fsl_pcie_init_board(0);

	hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));

	if (hose) {
		u32 temp32;
		u8 uli_busno = hose->first_busno + 2;

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 * Device 1d has the first on-board memory BAR.
		 */
		pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
				PCI_BASE_ADDRESS_1, &temp32);

		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
			void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
					temp32, 4, 0);
			debug(" uli1572 read to %p\n", p);
			in_be32(p);
		}
	}
}

pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
	struct pci_controller * hose;
	u16 vendor, device;
	u8 header_type;
	pci_dev_t bdf;
	int i, bus, found_multi = 0;

	for (hose = hose_head; hose; hose = hose->next)
	{
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
		for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
#else
		for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
			for (bdf = PCI_BDF(bus,0,0);
#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
			     bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
#else
			     bdf < PCI_BDF(bus+1,0,0);
#endif
			     bdf += PCI_BDF(0,0,1))
			{
				if (!PCI_FUNC(bdf)) {
					pci_read_config_byte(bdf,
							     PCI_HEADER_TYPE,
							     &header_type);

					found_multi = header_type & 0x80;
				} else {
					if (!found_multi)
						continue;
				}

				pci_read_config_word(bdf,
						     PCI_VENDOR_ID,
						     &vendor);
				pci_read_config_word(bdf,
						     PCI_DEVICE_ID,
						     &device);

				for (i=0; ids[i].vendor != 0; i++)
					if (vendor == ids[i].vendor &&
					    device == ids[i].device)
					{
						if (index <= 0)
							return bdf;

						index--;
					}
			}
	}

	return (-1);
}

static void qemu_chipset_init(void)
{
	u16 device, xbcs;
	int pam, i;

	/*
	 * i440FX and Q35 chipset have different PAM register offset, but with
	 * the same bitfield layout. Here we determine the offset based on its
	 * PCI device ID.
	 */
	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
	i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
	pam = i440fx ? I440FX_PAM : Q35_PAM;

	/*
	 * Initialize Programmable Attribute Map (PAM) Registers
	 *
	 * Configure legacy segments C/D/E/F to system RAM
	 */
	for (i = 0; i < PAM_NUM; i++)
		pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);

	if (i440fx) {
		/*
		 * Enable legacy IDE I/O ports decode
		 *
		 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
		 * However Linux ata_piix driver does sanity check on these two
		 * registers to see whether legacy ports decode is turned on.
		 * This is to make Linux ata_piix driver happy.
		 */
		pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
		pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);

		/* Enable I/O APIC */
		pci_read_config16(PIIX_ISA, XBCS, &xbcs);
		xbcs |= APIC_EN;
		pci_write_config16(PIIX_ISA, XBCS, xbcs);

		enable_pm_piix();
	} else {
		/* Configure PCIe ECAM base address */
		pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
				   CONFIG_PCIE_ECAM_BASE | BAR_EN);

		enable_pm_ich9();
	}

#ifdef CONFIG_QFW
	qemu_fwcfg_init(&fwcfg_x86_ops);
#endif
}

static int get_pcie_bar(u32 *base, u32 *len)
{
	pci_dev_t dev = PCI_BDF(0, 0, 0);
	u32 pciexbar_reg;

	*base = 0;
	*len = 0;

	pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);

	if (!(pciexbar_reg & (1 << 0)))
		return 0;

	switch ((pciexbar_reg >> 1) & 3) {
	case 0: /* 256MB */
		*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
				(1 << 28));
		*len = 256 * 1024 * 1024;
		return 1;
	case 1: /* 128M */
		*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
				(1 << 28) | (1 << 27));
		*len = 128 * 1024 * 1024;
		return 1;
	case 2: /* 64M */
		*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
				(1 << 28) | (1 << 27) | (1 << 26));
		*len = 64 * 1024 * 1024;
		return 1;
	}

	return 0;
}

/**
 * pciinfo() - Show a list of devices on the PCI bus
 *
 * Show information about devices on PCI bus. Depending on @short_pci_listing
 * the output will be more or less exhaustive.
 *
 * @bus_num: The number of the bus to be scanned
 * @short_pci_listing: true to use short form, showing only a brief header
 * for each device
 */
void pciinfo(int bus_num, int short_pci_listing)
{
	struct pci_controller *hose = pci_bus_to_hose(bus_num);
	int device;
	int function;
	unsigned char header_type;
	unsigned short vendor_id;
	pci_dev_t dev;
	int ret;

	if (!hose)
		return;

	pciinfo_header(bus_num, short_pci_listing);

	for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
		header_type = 0;
		vendor_id = 0;
		for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
		     function++) {
			/*
			 * If this is not a multi-function device, we skip
			 * the rest.
			 */
			if (function && !(header_type & 0x80))
				break;

			dev = PCI_BDF(bus_num, device, function);

			if (pci_skip_dev(hose, dev))
				continue;

			ret = pci_read_config_word(dev, PCI_VENDOR_ID,
						   &vendor_id);
			if (ret)
				goto error;
			if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
				continue;

			if (!function) {
				pci_read_config_byte(dev, PCI_HEADER_TYPE,
						     &header_type);
			}

			if (short_pci_listing) {
				printf("%02x.%02x.%02x   ", bus_num, device,
				       function);
				pci_header_show_brief(dev);
			} else {
				printf("\nFound PCI device %02x.%02x.%02x:\n",
				       bus_num, device, function);
				pci_header_show(dev);
			}
		}
	}

	return;
error:
	printf("Cannot read bus configuration: %d\n", ret);
}

static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
	int offset, int len, u32 val) {

	/*
	 * 440SPE implements only one function per port
	 */
	if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
		return 0;

	devfn = PCI_BDF(0,0,0);
	offset += devfn << 4;

	switch (len) {
	case 1:
		out_8(hose->cfg_data + offset, val);
		break;
	case 2:
		out_le16((u16 *)(hose->cfg_data + offset), val);
		break;
	default:
		out_le32((u32 *)(hose->cfg_data + offset), val);
		break;
	}
	return 0;
}

void eepro100_srom_load (unsigned short *destination)
{
    int count;
    struct eth_device onboard_dev;
#ifdef DEBUG
    int lr = 0;
    printf ("eepro100_srom_download:\n");
#endif

    /* get onboard network iobase */
    pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0,
		 &onboard_dev.iobase);
    onboard_dev.iobase &= ~0xf;

    memset (destination, 0x65, 128);

    for (count=0; count < 0x40; count++)
    {
	*destination++ = read_eeprom (struct eth_device*)&onboard_dev,
		 count, EE_ADDR_BITS);
#ifdef DEBUG
	printf ("%04x ", *(destination - 1));
	if (lr++ == 7)
	{
	    printf("\n");
	    lr = 0;
	}
#endif
    }
}

void pci_assign_irqs(int bus, int device, u8 irq[4])
{
    pci_dev_t bdf;
    int func;
    u16 vendor;
    u8 pin, line;

    for (func = 0; func < 8; func++) {
        bdf = PCI_BDF(bus, device, func);
        vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
        if (vendor == 0xffff || vendor == 0x0000)
            continue;

        pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);

        /* PCI spec says all values except 1..4 are reserved */
        if ((pin < 1) || (pin > 4))
            continue;

        line = irq[pin - 1];
        if (!line)
            continue;

        debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
              line, bus, device, func, 'A' + pin - 1);

        x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
    }
}

/* Config the VIA chip */
void mpc85xx_config_via(struct pci_controller *hose,
			pci_dev_t dev, struct pci_config_table *tab)
{
	pci_dev_t bridge;
	unsigned int cmdstat;

	/* Enable USB and IDE functions */
	pci_hose_write_config_byte(hose, dev, 0x48, 0x08);

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);

	/*
	 * Force the backplane P2P bridge to have a window
	 * open from 0x00000000-0x00001fff in PCI I/O space.
	 * This allows legacy I/O (i8259, etc) on the VIA
	 * southbridge to be accessed.
	 */
	bridge = PCI_BDF(0,BRIDGE_ID,0);
	pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
	pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
	pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
	pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
}

/* Test that we can use the swapcase device correctly */
static int dm_test_pci_swapcase(struct unit_test_state *uts)
{
	struct udevice *emul, *swap;
	ulong io_addr, mem_addr;
	char *ptr;

	/* Check that asking for the device automatically fires up PCI */
	ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul));
	ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
	ut_assert(device_active(swap));

	/* First test I/O */
	io_addr = dm_pci_read_bar32(swap, 0);
	outb(2, io_addr);
	ut_asserteq(2, inb(io_addr));

	/*
	 * Now test memory mapping - note we must unmap and remap to cause
	 * the swapcase emulation to see our data and response.
	 */
	mem_addr = dm_pci_read_bar32(swap, 1);
	ptr = map_sysmem(mem_addr, 20);
	strcpy(ptr, "This is a TesT");
	unmap_sysmem(ptr);

	ptr = map_sysmem(mem_addr, 20);
	ut_asserteq_str("tHIS IS A tESt", ptr);
	unmap_sysmem(ptr);

	return 0;
}

void pci_target_init(struct pci_controller *hose)
{
    /* First do 440EP(x) common setup */
    __pci_target_init(hose);

    /*
     * Set up Configuration registers for on-board NEC uPD720101 USB
     * controller.
     */
    pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
}

void host_bridge_init (void)
{
	/* The bridge chip is at a fixed location. */
	pci_dev_t dev = PCI_BDF (0, 10, 0);

	/* Set PCI Class code --
	   The primary side sees this class code at 0x08 in the
	   primary config space. This must be something other then a
	   bridge, or MS Windows starts doing weird stuff to me. */
	pci_write_config_dword (dev, 0x48, 0x04800000);

	/* Set subsystem ID --
	   The primary side sees this value at 0x2c. We set it here so
	   that the host can tell what sort of device this is:
	   We are a Picture Elements [0x12c5] JSE [0x008a]. */
	pci_write_config_dword (dev, 0x6c, 0x008a12c5);

	/* Downstream (Primary-to-Secondary) BARs are set up mostly
	   off. We need only the Memory-0 Bar so that the host can get
	   at the CSR region to set up tables and the lot. */

	/* Downstream Memory 0 setup (4K for CSR) */
	pci_write_config_dword (dev, 0xac, 0xfffff000);
	/* Downstream Memory 1 setup (off) */
	pci_write_config_dword (dev, 0xb0, 0x00000000);
	/* Downstream Memory 2 setup (off) */
	pci_write_config_dword (dev, 0xb4, 0x00000000);
	/* Downstream Memory 3 setup (off) */
	pci_write_config_dword (dev, 0xb8, 0x00000000);

	/* Upstream (Secondary-to-Primary) BARs are used to get at
	   host memory from the JSE card. Create two regions: a small
	   one to manage individual word reads/writes, and a larger
	   one for doing bulk frame moves. */

	/* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
	pci_write_config_dword (dev, 0xc4, 0xfffff000);
	/* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
	pci_write_config_dword (dev, 0xc8, 0xfffff000);

	/* Upstream Memory 2 (BAR4) uses page translation, and is set
	   up in CCR1. Configure for 4K pages. */

	/* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
	   bit as well, so we are done configuring after this
	   point. Therefore, this must be the last step.

	   CC1[15:12]= 0  (disable I2O message unit)
	   CC1[11:8] = 0x5 (4K page size)
	   CC0[11]   = 1  (Secondary Clock Disable: disable clock)
	   CC0[10]   = 0  (Primary Access Lockout: allow primary access)
	 */
	pci_write_config_dword (dev, 0xcc, 0x05000800);
}

void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
{
	u16 temp16;
	u32 temp32;
	int enabled, r, inbound = 0;
	u16 ltssm;
	u8 temp8, pcie_cap;
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
	struct pci_region *reg = hose->regions + hose->region_count;
	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);

	/* Initialize ATMU registers based on hose regions and flags */
	volatile pot_t *po = &pci->pot[1];	/* skip 0 */
	volatile pit_t *pi = &pci->pit[2];	/* ranges from: 3 to 1 */

	u64 out_hi = 0, out_lo = -1ULL;
	u32 pcicsrbar, pcicsrbar_sz;

#ifdef DEBUG
	int neg_link_w;
#endif

	pci_setup_indirect(hose, cfg_addr, cfg_data);

	/* Handle setup of outbound windows first */
	for (r = 0; r < hose->region_count; r++) {
		unsigned long flags = hose->regions[r].flags;
		u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);

		flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
		if (flags != PCI_REGION_SYS_MEMORY) {
			u64 start = hose->regions[r].bus_start;
			u64 end = start + hose->regions[r].size;

			out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
			out_be32(&po->potar, start >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
			out_be32(&po->potear, start >> 44);
#else
			out_be32(&po->potear, 0);
#endif
			if (hose->regions[r].flags & PCI_REGION_IO) {
				out_be32(&po->powar, POWAR_EN | sz |
					POWAR_IO_READ | POWAR_IO_WRITE);
			} else {
				out_be32(&po->powar, POWAR_EN | sz |
					POWAR_MEM_READ | POWAR_MEM_WRITE);
				out_lo = min(start, out_lo);
				out_hi = max(end, out_hi);
			}
			po++;
		}
	}

/*
 * Subroutine:  pciinfo
 *
 * Description: Show information about devices on PCI bus.
 *                Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
 *                the output will be more or less exhaustive.
 *
 * Inputs:    bus_no        the number of the bus to be scanned.
 *
 * Return:      None
 *
 */
void pciinfo(u32 BusNum)
{
    int Device;
    int Function;
    unsigned char HeaderType;
    unsigned short VendorID;
    pci_dev_t dev;
    int ShortPCIListing;

    printf("Scanning PCI devices on bus %d\r\n", BusNum);
    ShortPCIListing = 0;
    if (ShortPCIListing)
    {
        printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\r\n");
        printf("_____________________________________________________________\r\n");
    }

    for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++)
    {
        HeaderType = 0;
        VendorID = 0;
        for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++)
        {
            /*
             * If this is not a multi-function device, we skip the rest.
             */
            if (Function && !(HeaderType & 0x80))
                break;

            dev = PCI_BDF(BusNum, Device, Function);

            pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
            if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
                continue;

            if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);

            if (ShortPCIListing)
            {
                printf("%02x %02x %02x   ", BusNum, Device, Function);
                pci_header_show_brief(dev);
            }
            else
            {
                printf("\nFound PCI device %02x %02x %02x:\r\n",
                           BusNum, Device, Function);
                pci_header_show(dev);
            }
        }
    }
}

/*
 * Unlock the configuration bit so that the host system can begin booting
 *
 * This should be used after you have:
 * 1) Called mpc83xx_pci_init()
 * 2) Set up your inbound translation windows to the appropriate size
 */
void mpc83xx_pcislave_unlock(int bus)
{
    struct pci_controller *hose = &pci_hose[bus];
    u32 dev;
    u16 reg16;

    /* Unlock configuration lock in PCI function configuration register */
    dev = PCI_BDF(hose->first_busno, 0, 0);
    pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
    reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
    pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);

    /* The configuration bit is now unlocked, so we can scan the bus */
    hose->last_busno = pci_hose_scan(hose);
}

int bridge_silicon_revision(void)
{
	if (bridge_revision_id < 0) {
		struct cpuid_result result;
		uint8_t stepping, bridge_id;
		pci_dev_t dev;

		result = cpuid(1);
		stepping = result.eax & 0xf;
		dev = PCI_BDF(0, 0, 0);
		bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
		bridge_revision_id = bridge_id | stepping;
	}

	return bridge_revision_id;
}

static int broadwell_pch_early_init(struct udevice *dev)
{
	struct gpio_desc desc;
	struct udevice *bus;
	pci_dev_t bdf;
	int ret;

	dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1);

	dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1);
	dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
	dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
	dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN);

	/* Enable IOAPIC */
	writew(0x1000, RCB_REG(OIC));
	/* Read back for posted write */
	readw(RCB_REG(OIC));

	/* Set HPET address and enable it */
	clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);
	/* Read back for posted write */
	readl(RCB_REG(HPTC));
	/* Enable HPET to start counter */
	setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0);

	setbits_le32(RCB_REG(GCS), 1 << 5);

	/*
	 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
	 * to prevent possible brownout. This will cause the GPIOs to be set
	 * up if it has not been done already.
	 */
	ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc,
				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
	if (ret)
		return ret;

	/* 8.14 Additional PCI Express Programming Steps, step #1 */
	bdf = PCI_BDF(0, 0x1c, 0);
	bus = pci_get_controller(dev);
	pci_bus_clrset_config32(bus, bdf, 0xf4, 0x60, 0);
	pci_bus_clrset_config32(bus, bdf, 0xf4, 0x80, 0x80);
	pci_bus_clrset_config32(bus, bdf, 0xe2, 0x30, 0x30);

	return 0;
}

/*
 * Configure the internal clock of both SIO HS-UARTs, if they are enabled
 * via FSP
 */
int arch_cpu_init_dm(void)
{
	struct udevice *dev;
	void *base;
	int ret;
	int i;

	/* Loop over the 2 HS-UARTs */
	for (i = 0; i < 2; i++) {
		ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev);
		if (!ret) {
			base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
					      PCI_REGION_MEM);
			hsuart_clock_set(base);
		}
	}

	return 0;
}

int eepro100_srom_store (unsigned short *source)
{
    int count;
    struct eth_device onboard_dev;

    /* get onboard network iobase */
    pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0,
		 &onboard_dev.iobase);
    onboard_dev.iobase &= ~0xf;

    source[63] = eepro100_srom_checksum (source);

    for (count=0; count < EE_SIZE; count++)
    {
    if ( eepro100_write_eeprom ((struct eth_device*)&onboard_dev,
	     count, EE_ADDR_BITS, SROM_SHORT(source)) == -1 )
	return -1;
    source++;
    }
    return 0;
}