static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
    ScrnInfoPtr pScrn = b->pScrn;
    RADEONInfoPtr info = RADEONPTR(pScrn);
    unsigned char *RADEONMMIO = info->MMIO;
    
    uint32_t status;


    if((count!=4))
    {
    xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to access VIP bus with non-stadard transaction length\n");
    return FALSE;
    }
    
    RADEONWaitForFifo(pScrn, 2);
    OUTREG(RADEON_VIPH_REG_ADDR, address & (~0x2000));
    while(VIP_BUSY == (status = RADEONVIP_idle(b)));
    
    if(VIP_IDLE != status) return FALSE;
    
    RADEONWaitForFifo(pScrn, 2);
    switch(count){
        case 4:
             OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer);
             break;
        }
    write_mem_barrier();
    while(VIP_BUSY == (status = RADEONVIP_idle(b)));
    if(VIP_IDLE != status) return FALSE;
    return TRUE;
}

static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
    ScrnInfoPtr pScrn = b->pScrn;
    RADEONInfoPtr info = RADEONPTR(pScrn);
    unsigned char *RADEONMMIO = info->MMIO;
    
    uint32_t status;
	uint32_t i;

    RADEONWaitForFifo(pScrn, 2);
    OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000);
    while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));

    
    if(VIP_IDLE != status){
		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
		return FALSE;
	}
    
	RADEONWaitForFifo(pScrn, 2);
	for (i = 0; i < count; i+=4)
	{
		OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i));
    	write_mem_barrier();
		while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
    	if(VIP_IDLE != status)
		{
    		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write to VIPH_REG_DATA\n");
			return FALSE;
	 	}
	}
				
    return TRUE;
}

static void
I830ShowCursor(ScrnInfoPtr pScrn)
{
   I830Ptr pI830 = I830PTR(pScrn);
   CARD32 temp;

   DPRINTF(PFX, "I830ShowCursor\n");
   DPRINTF(PFX,
	   "Value of CursorMem.Physical is %x, "
	   " Value of CursorMem.Start is %x ",
	   pI830->CursorMem.Physical, pI830->CursorMem.Start);

   pI830->cursorOn = TRUE;
   if (IS_MOBILE(pI830)) {
      temp = INREG(CURSOR_A_CONTROL);
      temp &= ~CURSOR_MODE;
      temp |= CURSOR_MODE_64_4C_AX;
      /* Need to set mode, then address. */
      OUTREG(CURSOR_A_CONTROL, temp);
      OUTREG(CURSOR_A_BASE, pI830->CursorMem.Physical);
   } else {
      temp = INREG(CURSOR_CONTROL);
      temp |= CURSOR_ENABLE;
      OUTREG(CURSOR_CONTROL, temp);
   }
}

static int
MGASetPortAttributeOverlay(
    ScrnInfoPtr pScrn,
    Atom attribute,
    INT32 value,
    pointer data
) {
    MGAPtr pMga = MGAPTR(pScrn);
    MGAPortPrivPtr pPriv = pMga->portPrivate;

    CHECK_DMA_QUIESCENT(pMga, pScrn);

    if(attribute == xvBrightness) {
        if((value < -128) || (value > 127))
            return BadValue;
        pPriv->brightness = value;
        OUTREG(MGAREG_BESLUMACTL, ((pPriv->brightness & 0xff) << 16) |
               (pPriv->contrast & 0xff));
    } else if(attribute == xvContrast) {
        if((value < 0) || (value > 255))
            return BadValue;
        pPriv->contrast = value;
        OUTREG(MGAREG_BESLUMACTL, ((pPriv->brightness & 0xff) << 16) |
               (pPriv->contrast & 0xff));
    } else if(attribute == xvColorKey) {
        pPriv->colorKey = value;
        outMGAdac(0x55, (pPriv->colorKey & pScrn->mask.red) >>
                  pScrn->offset.red);
        outMGAdac(0x56, (pPriv->colorKey & pScrn->mask.green) >>
                  pScrn->offset.green);
        outMGAdac(0x57, (pPriv->colorKey & pScrn->mask.blue) >>
                  pScrn->offset.blue);
        REGION_EMPTY(pScrn->pScreen, &pPriv->clip);
    } else if(attribute == xvDoubleBuffer) {

/* Set cursor foreground and background colors. */
static void R128SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
{
    R128InfoPtr   info      = R128PTR(pScrn);
    unsigned char *R128MMIO = info->MMIO;

    OUTREG(R128_CUR_CLR0, bg);
    OUTREG(R128_CUR_CLR1, fg);
}

static void
Neo2097SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y, int w, int h)
{
    NEOPtr nPtr = NEOPTR(pScrn);

    WAIT_ENGINE_IDLE();
    OUTREG(NEOREG_DSTSTARTOFF, (y<<16) | (x & 0xffff));
    OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
}

static void
Neo2070SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y, int w, int h)
{
    NEOPtr nPtr = NEOPTR(pScrn);
    NEOACLPtr nAcl = NEOACLPTR(pScrn);

    WAIT_ENGINE_IDLE();
    OUTREG(NEO2070_XYEXT, ((h-1)<<16) | ((w-1) & 0xffff));
    OUTREG(NEO2070_DSTSTART, (y * nAcl->Pitch) + (x * nAcl->PixelWidth));
}

static UINT32 i810_getscl(struct i2c_driver_t *st)
{
	UCHAR *mmio = st->mmio_start_virtual;
	UINT32 val;

	OUTREG(mmio + st->ddc_base, SCL_DIR_MASK);
	OUTREG(mmio + st->ddc_base, 0);
	val = INREG(mmio + st->ddc_base);
	return ((val & SCL_VAL_IN) != 0);
}

static void
i830_dvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
		  DisplayModePtr adjusted_mode)
{
    ScrnInfoPtr		    scrn = output->scrn;
    intel_screen_private    *intel = intel_get_screen_private(scrn);
    xf86CrtcPtr	    crtc = output->crtc;
    I830CrtcPrivatePtr	    intel_crtc = crtc->driver_private;
    I830OutputPrivatePtr    intel_output = output->driver_private;
    struct _I830DVODriver   *drv = intel_output->i2c_drv;
    int			    pipe = intel_crtc->pipe;
    uint32_t		    dvo;
    unsigned int	    dvo_reg = drv->dvo_reg, dvo_srcdim_reg;
    int			    dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;

    switch (dvo_reg) {
    case DVOA:
    default:
	dvo_srcdim_reg = DVOA_SRCDIM;
	break;
    case DVOB:
	dvo_srcdim_reg = DVOB_SRCDIM;
	break;
    case DVOC:
	dvo_srcdim_reg = DVOC_SRCDIM;
	break;
    }

    intel_output->i2c_drv->vid_rec->mode_set(intel_output->i2c_drv->dev_priv,
					     mode, adjusted_mode);

    /* Save the data order, since I don't know what it should be set to. */
    dvo = INREG(dvo_reg) & (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
    dvo |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | DVO_BLANK_ACTIVE_HIGH;

    if (pipe == 1)
	dvo |= DVO_PIPE_B_SELECT;
    dvo |= DVO_PIPE_STALL;
    if (adjusted_mode->Flags & V_PHSYNC)
	dvo |= DVO_HSYNC_ACTIVE_HIGH;
    if (adjusted_mode->Flags & V_PVSYNC)
	dvo |= DVO_VSYNC_ACTIVE_HIGH;

    OUTREG(dpll_reg, INREG(dpll_reg) | DPLL_DVO_HIGH_SPEED);

    /*OUTREG(DVOB_SRCDIM,
      (adjusted_mode->HDisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
      (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
    OUTREG(dvo_srcdim_reg,
	   (adjusted_mode->HDisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	   (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));
    /*OUTREG(DVOB, dvo);*/
    OUTREG(dvo_reg, dvo);
}

static int intelfb_gpio_getsda(void *data)
{
	struct intelfb_i2c_chan *chan = data;
	struct intelfb_info *dinfo = chan->dinfo;
	u32 val;

	OUTREG(chan->reg, SDA_DIR_MASK);
	OUTREG(chan->reg, 0);
	val = INREG(chan->reg);
	return ((val & SDA_VAL_IN) != 0);
}

static void
I830SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
{
   I830Ptr pI830 = I830PTR(pScrn);

   DPRINTF(PFX, "I830SetCursorColors\n");

   OUTREG(CURSOR_A_PALETTE0, bg & 0x00ffffff);
   OUTREG(CURSOR_A_PALETTE1, fg & 0x00ffffff);
   OUTREG(CURSOR_A_PALETTE2, fg & 0x00ffffff);
   OUTREG(CURSOR_A_PALETTE3, bg & 0x00ffffff);
}

static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
{		
	OUTREG(GPIOPAD_MASK, 0x0001ffff);
	OUTREG(GPIOPAD_EN, 0x00000400);
	OUTREG(GPIOPAD_A, 0x00000000);		
        OUTREG(ZV_LCDPAD_MASK, 0x00000000);
        OUTREG(ZV_LCDPAD_EN, 0x00000000);
      	OUTREG(ZV_LCDPAD_A, 0x00000000); 	
	OUTREG(GPIO_VGA_DDC, 0x00030000);
	OUTREG(GPIO_DVI_DDC, 0x00000000);
	OUTREG(GPIO_MONID, 0x00030000);
	OUTREG(GPIO_CRT2_DDC, 0x00000000);
}

bool
Mach64_LoadCursorImage(int width, int height, uint8* andMask, uint8* xorMask)
{
	SharedInfo& si = *gInfo.sharedInfo;

	if (andMask == NULL || xorMask == NULL)
		return false;

	uint16* fbCursor = (uint16*)((addr_t)si.videoMemAddr + si.cursorOffset);

	// Initialize the hardware cursor as completely transparent.

	memset(fbCursor, 0xaa, CURSOR_BYTES);

	// Now load the AND & XOR masks for the cursor image into the cursor
	// buffer.  Note that a particular bit in these masks will have the
	// following effect upon the corresponding cursor pixel:
	//	AND  XOR	Result
	//	 0    0		 White pixel
	//	 0    1		 Black pixel
	//	 1    0		 Screen color (for transparency)
	//	 1    1		 Reverse screen color to black or white

	for (int row = 0; row < height; row++) {
		for (int colByte = 0; colByte < width / 8; colByte++) {
			// Convert the 8 bit AND and XOR masks into a 16 bit mask containing
			// pairs of the bits from the AND and XOR maks.

			uint8 andBits = *andMask++;
			uint8 xorBits = *xorMask++;
			uint16 cursorBits = 0;

			for (int j = 0; j < 8; j++) {
				cursorBits <<= 2;
				cursorBits |= ((andBits & 0x01) << 1);
				cursorBits |= (xorBits & 0x01);
				andBits >>= 1;
				xorBits >>= 1;
			}

			fbCursor[row * 8 + colByte] = cursorBits;
		}
	}

	// Set the cursor colors which are white background and black foreground.

	OUTREG(CUR_CLR0, ~0);
	OUTREG(CUR_CLR1, 0);

	return true;
}

static void
i830_dvo_restore(xf86OutputPtr output)
{
    ScrnInfoPtr		    scrn = output->scrn;
    intel_screen_private    *intel = intel_get_screen_private(scrn);
    I830OutputPrivatePtr    intel_output = output->driver_private;
    void *		    dev_priv = intel_output->i2c_drv->dev_priv;

    (*intel_output->i2c_drv->vid_rec->restore)(dev_priv);

    OUTREG(DVOA, intel->saveDVOA);
    OUTREG(DVOB, intel->saveDVOB);
    OUTREG(DVOC, intel->saveDVOC);
}

static void
Neo2097SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn,
                                    int srcX, int srcY,
                                    int dstX, int dstY,
                                    int w, int h)
{
    NEOPtr nPtr = NEOPTR(pScrn);
    NEOACLPtr nAcl = NEOACLPTR(pScrn);

    if ((dstY < srcY) || ((dstY == srcY) && (dstX < srcX))) {
        /* start with upper left corner */
        WAIT_ENGINE_IDLE();
        OUTREG(NEOREG_BLTCNTL, nAcl->tmpBltCntlFlags);
        OUTREG(NEOREG_SRCSTARTOFF, (srcY<<16) | (srcX & 0xffff));
        OUTREG(NEOREG_DSTSTARTOFF, (dstY<<16) | (dstX & 0xffff));
        OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
    }
    else {
        /* start with lower right corner */
        WAIT_ENGINE_IDLE();
        OUTREG(NEOREG_BLTCNTL, (nAcl->tmpBltCntlFlags | NEO_BC0_X_DEC
                                | NEO_BC0_DST_Y_DEC
                                | NEO_BC0_SRC_Y_DEC));
        OUTREG(NEOREG_SRCSTARTOFF, ((srcY+h-1)<<16) | ((srcX+w-1) & 0xffff));
        OUTREG(NEOREG_DSTSTARTOFF, ((dstY+h-1)<<16) | ((dstX+w-1) & 0xffff));
        OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
    }
}

static void
Neo2097SubsequentScanlineImageWriteRect(
    ScrnInfoPtr pScrn,
    int x, int y, int w, int h,
    int skipleft
) {
    NEOPtr nPtr = NEOPTR(pScrn);
    NEOACLPtr nAcl = NEOACLPTR(pScrn);

    WAIT_ENGINE_IDLE();
    OUTREG(NEOREG_BLTCNTL, nAcl->tmpBltCntlFlags);
    OUTREG(NEOREG_SRCSTARTOFF, 0);
    OUTREG(NEOREG_DSTSTARTOFF, (y << 16) | (x & 0xffff));
    OUTREG(NEOREG_XYEXT, (h << 16) | w);
}

// reset VIP
void Radeon_VIPReset( 
	device_info *di, bool lock )
{
	vuint8 *regs = di->regs;

	if( lock )
		ACQUIRE_BEN( di->si->cp.lock );

	Radeon_WaitForFifo( di, 5 ); // Radeon_WaitForIdle( di, false, false );
	switch(di->asic){
	    case rt_r200:
	    case rt_rs200:
	    case rt_rv200:
	    case rt_rs100:
		case rt_rv100:
		case rt_r100:
	    OUTREG( regs, RADEON_VIPH_CONTROL, 4 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
			RADEON_VIPH_CONTROL_VIPH_DMA_MODE |	RADEON_VIPH_CONTROL_VIPH_EN ); // slowest, timeout in 16 phases
	    OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | 
	    	RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
	    OUTREG( regs, RADEON_VIPH_DV_LAT, 
	    		0xff |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT)); // set timeslice
	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x151);
	    OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
	default:
		    OUTREG( regs, RADEON_VIPH_CONTROL, 9 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
				RADEON_VIPH_CONTROL_VIPH_DMA_MODE |	RADEON_VIPH_CONTROL_VIPH_EN ); // slowest, timeout in 16 phases
	    OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | 
		    	RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
	    OUTREG( regs, RADEON_VIPH_DV_LAT, 
			    0xff |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT)); // set timeslice
	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x0);
	    OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
	    break;

	} 
		
	if( lock )
		RELEASE_BEN( di->si->cp.lock );
}

// copy from graphics memory to other memory via DMA
// 	src		- offset in graphics mem
//	target	- target address
//	size	- number of bytes to copy
//	lock_mem - true, if memory is not locked
//	contiguous - true, if memory is physically contiguous (implies lock_mem=false)
status_t Radeon_DMACopy( 
	device_info *di, uint32 src, char *target, size_t size, bool lock_mem, bool contiguous )
{
	status_t res;
	
	/*SHOW_FLOW( 0, "src=%ld, target=%p, size=%ld, lock_mem=%d, contiguous=%d",
		src, target, size, lock_mem, contiguous );*/
	
	res =  Radeon_PrepareDMA( di, src, target, size, lock_mem, contiguous );
	if( res != B_OK )
		return res;
		
	//SHOW_FLOW0( 0, "2" );

	OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start +
		di->dma_desc_offset );
		
	res = acquire_sem_etc( di->dma_sem, 1, B_RELATIVE_TIMEOUT, 1000000 );
	
	// be sure that transmission is really finished
	while( (INREG( di->regs, RADEON_DMA_VID_STATUS ) & RADEON_DMA_STATUS_ACTIVE) != 0 ) {
		SHOW_FLOW0( 0, "DMA transmission still active" );
		snooze( 1000 );
	}
		
	Radeon_FinishDMA( di, src, target, size, lock_mem, contiguous );
	
	//SHOW_FLOW0( 0, "3" );
	
	return res;
}

// cleanup PCI GART
void Radeon_CleanupPCIGART( device_info *di )
{
	vuint8 *regs = di->regs;

	SHOW_FLOW0( 3, "" );

	// perhaps we should wait for FIFO space before messing around with registers, but
	// 1. I don't want to add all the sync stuff to the kernel driver
	// 2. I doubt that these regs are buffered by FIFO
	// but still: in worst case CP has written some commands to register FIFO,
	// which can do any kind of nasty things

	// disable CP BM
	OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
	// read-back for flushing
	INREG( regs, RADEON_CP_CSQ_CNTL );

	// disable bus mastering
	OUTREGP( regs, RADEON_BUS_CNTL, RADEON_BUS_MASTER_DIS, ~RADEON_BUS_MASTER_DIS );
	// disable PCI GART
	OUTREGP( regs, RADEON_AIC_CNTL, 0, ~RADEON_PCIGART_TRANSLATE_EN );

	destroyGATT( &di->pci_gart );
	destroyGARTBuffer( &di->pci_gart );
}

static void
MGAStopVideo(ScrnInfoPtr pScrn, pointer data, Bool shutdown)
{
    MGAPtr pMga = MGAPTR(pScrn);
    MGAPortPrivPtr pPriv = pMga->portPrivate;

    if(pMga->TexturedVideo) return;

    REGION_EMPTY(pScrn->pScreen, &pPriv->clip);

    if(shutdown) {
        if(pPriv->videoStatus & CLIENT_VIDEO_ON)
            OUTREG(MGAREG_BESCTL, 0);
        if(pPriv->linear) {
            xf86FreeOffscreenLinear(pPriv->linear);
            pPriv->linear = NULL;
        }
        pPriv->videoStatus = 0;
    } else {
        if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
            pPriv->videoStatus |= OFF_TIMER;
            pPriv->offTime = currentTime.milliseconds + OFF_DELAY;
        }
    }
}