int32_t uart_write_data (uint8_t *data, uint16_t size) {
    uint32_t cnt;
    int16_t  len_in_buf;

    if (size == 0) {
        return 0;
    }

    cnt = 0;
    while (size--) {
        len_in_buf = write_buffer.cnt_in - write_buffer.cnt_out;
        if (len_in_buf < BUFFER_SIZE) {
            write_buffer.data[write_buffer.idx_in++] = *data++;
            write_buffer.idx_in &= (BUFFER_SIZE - 1);
            write_buffer.cnt_in++;
            cnt++;
        }
    }

    // enable THRE interrupt
    LPC_USART->IER |= (1 << 1);

    if (!tx_in_progress) {
        // force THRE interrupt to start
        NVIC_SetPendingIRQ(UART_IRQn);
    }

    return cnt;
}

/*******************************************************************************
* Function Name  : uart_irq_handler
* Description    : Interrupt handle function
* Input          : - Uart: Select the USART or the UART peripheral.
* Output         : None
* Return         : None
*******************************************************************************/
void uart_irq_handler(const _Uart_Descriptor *Uart)
{
  //
  __hw_enter_interrupt();
  
  //
  if (*Uart->Ctrl && (*Uart->Ctrl)->DmaBufSize)
  {
    if (USART_GetITStatus(Uart->UARTx, USART_IT_IDLE) != RESET)                          // Idle line
    {
      NVIC_SetPendingIRQ(Uart->DMAx_IRQn);
      USART_ReceiveData(Uart->UARTx);
    }
  }
  else if (USART_GetITStatus(Uart->UARTx, USART_IT_RXNE) != RESET)                       // Received Data Ready to be Read
  {
    if (*Uart->Ctrl && ((*Uart->Ctrl)->RxCnt < (*Uart->Ctrl)->RxBufSize))
    {
      (*Uart->Ctrl)->RxBufPtr[(*Uart->Ctrl)->RxiPut++] = (char)USART_ReceiveData(Uart->UARTx);
      //lepton
      if(!(*Uart->Ctrl)->RxCnt){
        if(Uart->board_uart_info && Uart->board_uart_info->desc_r!=-1)
           __fire_io_int(ofile_lst[Uart->board_uart_info->desc_r].owner_pthread_ptr_read);
      }
      //lepton
      (*Uart->Ctrl)->RxCnt++;
      if ((*Uart->Ctrl)->RxiPut >= (*Uart->Ctrl)->RxBufSize) (*Uart->Ctrl)->RxiPut = 0;
      if (((*Uart->Ctrl)->HwCtrl & UART_HW_FLOW_CTRL_RX) && ((*Uart->Ctrl)->RxCnt > ((*Uart->Ctrl)->RxBufSize - (*Uart->Ctrl)->DmaBufSize))) uart_set_rx_hw_fc(Uart);
    }
    else USART_ClearITPendingBit(Uart->UARTx, USART_IT_RXNE);
    #ifdef _UART_OS_SUPPORT
      isr_evt_set((*Uart->Ctrl)->Event, (*Uart->Ctrl)->Task);
    #endif
  }

  if (USART_GetITStatus(Uart->UARTx, USART_IT_TXE) != RESET)                             // Transmit Data Register Empty
  {
    if (*Uart->Ctrl && (*Uart->Ctrl)->TxCnt)
    {
      USART_SendData(Uart->UARTx, (*Uart->Ctrl)->TxBufPtr[(*Uart->Ctrl)->TxiGet++]);
      (*Uart->Ctrl)->TxCnt--;
      if ((*Uart->Ctrl)->TxiGet >= (*Uart->Ctrl)->TxBufSize) (*Uart->Ctrl)->TxiGet = 0;
    }
    else{
      USART_ITConfig(Uart->UARTx, USART_IT_TXE, DISABLE);
      //lepton
        if(Uart->board_uart_info && Uart->board_uart_info->desc_w!=-1)
           __fire_io_int(ofile_lst[Uart->board_uart_info->desc_w].owner_pthread_ptr_write);
      //lepton
    }
  }

  if (USART_GetITStatus(Uart->UARTx, USART_IT_TC) != RESET)                              // Transmission complete
  {
    if (*Uart->Ctrl && ((*Uart->Ctrl)->HwCtrl & UART_HALF_DUPLEX)) uart_tx_disable(Uart);
    USART_ClearITPendingBit(Uart->UARTx, USART_IT_TC);
  }
  //
  __hw_leave_interrupt();
}

int main(void) {
	//initialize everything

	NVIC_SetPriority(EINT3_IRQn,0);
	NVIC_SetPriority(EINT1_IRQn,1);
	LPC_GPIOINT -> IO0IntEnR |= (1<<2);
	LPC_GPIO1 -> FIODIR |= LED0;
	LPC_GPIO1 -> FIODIR |= LED1;
	LPC_GPIO1 -> FIODIR |= LED2;
	NVIC_EnableIRQ(EINT1_IRQn);
	NVIC_EnableIRQ(EINT3_IRQn);
	LPC_GPIO1 -> FIOPIN = ~LED0;

	while(1){

		flag = ((~LPC_GPIO0 -> FIOPIN) & (1<<3)) == (1<<3);
		// Blink LED0
		LPC_GPIO1 -> FIOPIN ^= LED0;
		for(n=0;n<900000;n++);

		if(flag == 1) NVIC_SetPendingIRQ(EINT1_IRQn);


	}

	return 0;
}

void us_ticker_fire_interrupt(void)
{
    us_ticker_int_counter = 0;
    us_ticker_int_remainder = 0;

    NVIC_SetPendingIRQ(TPM2_IRQn);
}

uint32_t event_handler_push(async_event_t* p_evt)
{
    if (p_evt == NULL)
    {
        return NRF_ERROR_NULL;
    }
    fifo_t* p_fifo = NULL;
    switch (p_evt->type)
    {
    case EVENT_TYPE_GENERIC:
    case EVENT_TYPE_PACKET:
    case EVENT_TYPE_SET_FLAG:
    case EVENT_TYPE_TIMER_SCH:
        p_fifo = &g_async_evt_fifo;
        break;
    case EVENT_TYPE_TIMER:
        p_fifo = &g_async_evt_fifo_ts;
        break;
    default:
        return NRF_ERROR_INVALID_PARAM;
    }
    uint32_t result = fifo_push(p_fifo, p_evt);
    if (result != NRF_SUCCESS)
    {
        return result;
    }

    /* trigger IRQ */
    NVIC_SetPendingIRQ(EVENT_HANDLER_IRQ);

    return NRF_SUCCESS;
}

/**@brief   Function for receiving callbacks from the micro-esb library.
 */
static void uesb_event_handler(void)
{
    uint32_t rf_interrupts;

    uesb_get_clear_interrupts(&rf_interrupts);

    if(rf_interrupts & UESB_INT_TX_FAILED_MSK)
    {
        // Transmit failed: flush buffer
        uesb_flush_tx();

        m_tx_attempts += 1;
        m_ut_state     = UT_STATE_RX;
    }
    if (rf_interrupts & UESB_INT_TX_SUCCESS_MSK)
    {
        uesb_payload_t payload;
        uint32_t       payload_len;
        
        // Successful transmission. Can now remove packet from our FIFO
        payload_len = sizeof(payload);
        fifo_get_pkt(&m_transmit_fifo, (uint8_t *) &payload, &payload_len);
        APP_ERROR_CHECK_BOOL(payload_len == sizeof(payload));
        
        m_tx_attempts = 0;
        m_ut_state    = UT_STATE_RX;
    }
    if(rf_interrupts & UESB_INT_RX_DR_MSK)
    {
        // Data reception is handled in a lower priority interrupt
        NVIC_SetPendingIRQ(UESB_RX_HANDLE_IRQn);
    }
}

void lp_ticker_set_interrupt(timestamp_t timestamp)
{
    uint32_t now = lp_ticker_read();
    wakeup_tick = timestamp;
    
    TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
    
    /**
     * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
     * Conditions in which delta is negative:
     * 1. Wrap around
     * 2. Newly scheduled alarm is behind now
     */ 
    //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
    int delta = (int) (timestamp - now);
    if (delta > 0) {
        cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
        lp_ticker_arm_cd();
    }
    else {
        cd_major_minor_clks = cd_minor_clks = 0;
        /**
         * This event was in the past. Set the interrupt as pending, but don't process it here.
         * This prevents a recurive loop under heavy load which can lead to a stack overflow.
         */  
        NVIC_SetPendingIRQ(timer3_modinit.irq_n);
    }
}

void test_arm_irq_vector_table(void)
{
	printk("Test Cortex-M3 IRQ installed directly in vector table\n");

	for (int ii = 0; ii < 3; ii++) {
		irq_enable(ii);
		_irq_priority_set(ii, 0, 0);
		k_sem_init(&sem[ii], 0, UINT_MAX);
	}

	zassert_true((k_sem_take(&sem[0], K_NO_WAIT) ||
		      k_sem_take(&sem[1], K_NO_WAIT) ||
		      k_sem_take(&sem[2], K_NO_WAIT)), NULL);

	for (int ii = 0; ii < 3; ii++) {
#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
			/* the QEMU does not simulate the
			 * STIR register: this is a workaround
			 */
		NVIC_SetPendingIRQ(ii);
#else
		NVIC->STIR = ii;
#endif
	}

	zassert_false((k_sem_take(&sem[0], K_NO_WAIT) ||
		       k_sem_take(&sem[1], K_NO_WAIT) ||
		       k_sem_take(&sem[2], K_NO_WAIT)), NULL);

}

/**
 * @brief  Sets Pending bit of an external interrupt.
 * @param  IRQn External interrupt number
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
 * @retval None
 */
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) {
	/* Check the parameters */
	assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

	/* Set interrupt pending */
	NVIC_SetPendingIRQ(IRQn);
}

void vApplicationTickHook( void )
{
	#if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )
	{
		/* Just to verify that the interrupt nesting behaves as expected,
		increment ulFPUInterruptNesting on entry, and decrement it on exit. */
		ulFPUInterruptNesting++;

		/* Fill the FPU registers with 0. */
		vRegTestClearFlopRegistersToParameterValue( 0UL );

		/* Trigger a timer 2 interrupt, which will fill the registers with a
		different value and itself trigger a timer 3 interrupt.  Note that the
		timers are not actually used.  The timer 2 and 3 interrupt vectors are
		just used for convenience. */
		NVIC_SetPendingIRQ( TIM2_IRQn );

		/* Ensure that, after returning from the nested interrupts, all the FPU
		registers contain the value to which they were set by the tick hook
		function. */
		configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 0UL ) );

		ulFPUInterruptNesting--;
	}
	#endif
}

void lp_ticker_fire_interrupt(void)
{
    // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
    //       This prevents a recursive loop under heavy load which can lead to a stack overflow.
    cd_major_minor_clks = cd_minor_clks = 0;
    NVIC_SetPendingIRQ(timer3_modinit.irq_n);
}

void event_handler_on_ts_begin(void)
{
    if (!fifo_is_empty(&g_async_evt_fifo) ||
        !fifo_is_empty(&g_async_evt_fifo_ts))
    {
        NVIC_SetPendingIRQ(EVENT_HANDLER_IRQ);
    }
}

void us_ticker_fire_interrupt(void)
{
    // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
    //       This prevents a recursive loop under heavy load which can lead to a stack overflow.
    NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);

    /* We can call ticker_irq_handler now. */
    NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
}

void evt_queue_add(radio_evt_type_t evt_type)
{
    uint32_t err_code;

    err_code = queue_add(&m_evt_queue, (uint8_t *) &evt_type);
    ASSUME_SUCCESS(err_code);

    NVIC_SetPendingIRQ(SWI0_IRQn);
}

void vIRQ_SetPendingIRQ(uint32_t irqn)
{
    if(__uvisor_mode == 0) {
        NVIC_SetPendingIRQ((IRQn_Type) irqn);
    }
    else {
        UVISOR_SVC(UVISOR_SVC_ID_IRQ_PEND_SET, "", irqn);
    }
}

void timeslot_queue_async_event(async_event_t* evt)
{
#if USE_SWI_FOR_PROCESSING
    NVIC_EnableIRQ(SWI0_IRQn);
    NVIC_SetPriority(SWI0_IRQn, 3);
    event_fifo_put(evt);
    NVIC_SetPendingIRQ(SWI0_IRQn);
#else
    /* execute immediately */
    async_event_execute(evt);
#endif
}

int16_t ll_plat_send_adv_report(adv_report_cb_t cb, struct adv_report *rpt)
{
    if (!cb || !rpt)
        return -EINVAL;

    adv_report_cb = cb;
    adv_report = rpt;

    NVIC_SetPendingIRQ(SWI0_IRQn);

    return 0;
}

//setint : set PMSG_TMR to expire once, in 'next' ms; set pending if next==0
void pmsg_setint(u16 next) {

	if (next == 0) {
		//directly set pending
		TIM_Cmd(PMSG_TMR, DISABLE);	//cancel current countdown
		NVIC_SetPendingIRQ(IRQN_PMSG);
		return;
	} else {
		PMSG_TMR->ARR = next;
		TIM_Cmd(PMSG_TMR, ENABLE);
	}
	return;
}

//******************************************************************************
void us_ticker_set(timestamp_t timestamp)
{
    US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0;  // disable timer
    current_cnt = (uint64_t)timestamp * ticks_per_us;
    US_TIMER->count32 = 0;
    US_TIMER->term_cnt32 = 0xFFFFFFFF;
    US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0;   // enable timer

    if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) {
        // The next timestamp has elapsed. Trigger the interrupt to handle it.
        NVIC_SetPendingIRQ(US_TIMER_IRQn);
    }
}

/**
\brief Test case: TC_MutexInterrupts
\details
- Call all mutex management functions from the ISR
*/
void TC_MutexInterrupts (void) {
  
  TST_IRQHandler = Mutex_IRQHandler;
  
  NVIC_EnableIRQ((IRQn_Type)SWI_HANDLER);
  
  Isr.Ex_Num = 0; /* Test: osMutexCreate */
  NVIC_SetPendingIRQ((IRQn_Type)SWI_HANDLER);
  __DMB();
  ASSERT_TRUE (ISR_MutexId == NULL);
  
  Isr.Ex_Num = 1; /* Test: osMutexWait */
  
  /* Create valid mutex, to be used for ISR function calls */
  ISR_MutexId = osMutexCreate  (osMutex (MutexIsr));
  ASSERT_TRUE (ISR_MutexId != NULL);
  
  if (ISR_MutexId != NULL) {
    NVIC_SetPendingIRQ((IRQn_Type)SWI_HANDLER);
    __DMB();
    ASSERT_TRUE (ISR_OsStat == osErrorISR);
  
    Isr.Ex_Num = 2; /* Test: osMutexRelease */
    NVIC_SetPendingIRQ((IRQn_Type)SWI_HANDLER);
    __DMB();
    ASSERT_TRUE (ISR_OsStat == osErrorISR);
    
    Isr.Ex_Num = 3; /* Test: osMutexDelete */
    NVIC_SetPendingIRQ((IRQn_Type)SWI_HANDLER);
    __DMB();
    ASSERT_TRUE (ISR_OsStat == osErrorISR);
    
    /* Delete mutex */
    ASSERT_TRUE (osMutexDelete (ISR_MutexId) == osOK);
  }
  
  NVIC_DisableIRQ((IRQn_Type)SWI_HANDLER);
}