/*******************************************************************************
* gstatsGetPortCounter3
*
* DESCRIPTION:
*        This routine gets a specific counter of the given port
*
* INPUTS:
*        port - the logical port number.
*        counter - the counter which will be read
*
* OUTPUTS:
*        statsData - points to 32bit data storage for the MIB counter
*
* RETURNS:
*        GT_OK      - on success
*        GT_FAIL    - on error
*
* COMMENTS:
*        This function supports Gigabit Switch and Spinnaker family
*
*******************************************************************************/
GT_STATUS gstatsGetPortCounter3
(
    IN  GT_QD_DEV        *dev,
    IN  GT_LPORT        port,
    IN  GT_STATS_COUNTERS3    counter,
    OUT GT_U32            *statsData
)
{
    GT_STATUS    retVal;
    GT_U8        hwPort;         /* physical port number         */

    DBG_INFO(("gstatsGetPortCounters3 Called.\n"));

    /* translate logical port to physical port */
    hwPort = GT_LPORT_2_PORT(port);

    /* check if device supports this feature */
    if((retVal = IS_VALID_API_CALL(dev,hwPort, DEV_RMON)) != GT_OK)
    {
        return retVal;
    }

    /* Only 88E6093 Switch supports this status. */
    if (!IS_IN_DEV_GROUP(dev,DEV_RMON_TYPE_3))
    {
        DBG_INFO(("GT_NOT_SUPPORTED\n"));
        return GT_NOT_SUPPORTED;
    }

    retVal = statsOperationPerform(dev,STATS_READ_COUNTER,hwPort,counter,(GT_VOID*)statsData);
    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed (statsOperationPerform returned GT_FAIL).\n"));
        return retVal;
    }

    DBG_INFO(("OK.\n"));
    return GT_OK;

}

/*******************************************************************************
* gpcsGetFCValue
*
* DESCRIPTION:
*        This routine retrieves Flow Control Value which will be used for Forcing 
*        Flow Control enabled or disabled.
*
* INPUTS:
*        port - the logical port number.
*
* OUTPUTS:
*        state - GT_TRUE if FC Force value is one (flow control enabled)
*                 GT_FALSE otherwise (flow control disabled)
*
* RETURNS:
*        GT_OK   - on success
*        GT_FAIL - on error
*        GT_NOT_SUPPORTED - if current device does not support this feature.
*        
* COMMENTS:
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gpcsGetFCValue
(
    IN  GT_QD_DEV    *dev,
    IN  GT_LPORT     port,
    OUT GT_BOOL      *state
)
{
    GT_U16          data;           /* Used to poll the SWReset bit */
    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U8           hwPort;         /* the physical port number     */

    DBG_INFO(("gpcsGetFCValue Called.\n"));

    /* check if the given Switch supports this feature. */
    if (!IS_IN_DEV_GROUP(dev,DEV_FC_WITH_VALUE))
    {
        DBG_INFO(("GT_NOT_SUPPORTED\n"));
        return GT_NOT_SUPPORTED;
    }

    /* translate LPORT to hardware port */
    hwPort = GT_LPORT_2_PORT(port);

    /* Get the FCValue bit.  */
    retVal = hwGetPortRegField(dev,hwPort, QD_REG_PCS_CONTROL,7,1,&data);

    /* translate binary to BOOL  */
    BIT_2_BOOL(data, *state);

    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed.\n"));
    }
    else
    {
        DBG_INFO(("OK.\n"));
    }
    /* return */
    return retVal;
}

/*******************************************************************************
* qdAccessRegs
*
* DESCRIPTION:
*       This function access registers through device interface
*        (like Marvell F2R on ethernet) by user, to be used by upper layers.
*
* INPUTS:
*   regList     - list of HW_DEV_RW_REG.
*     HW_DEV_RW_REG includes:
*     cmd - HW_REG_READ, HW_REG_WRITE, HW_REG_WAIT_TILL_0 or HW_REG_WAIT_TILL_1
*     addr - SMI Address
*     reg  - Register offset
*     data - INPUT,OUTPUT:Value in the Register or Bit number
*
* OUTPUTS:
*   regList     - list of HW_DEV_RW_REG.
*
* RETURNS:
*       GT_OK   - on success
*       GT_FAIL - on error
*
* COMMENTS:
*       None.
*
*******************************************************************************/
GT_STATUS qdAccessRegs
(
    IN  GT_QD_DEV    *dev,
    INOUT HW_DEV_REG_ACCESS *regList
)
{
  if((dev->accessMode == SMI_MULTI_ADDR_MODE) &&
     (dev->fgtHwAccessMod == HW_ACCESS_MODE_SMI))
  {
      if(qdMultiAddrAccess(dev, regList) != GT_TRUE)
      {
        return GT_FAIL;
      }
  }
  else
  {
    if ((IS_IN_DEV_GROUP(dev,DEV_RMGMT)) &&
        (dev->fgtHwAccess != NULL) &&
        (dev->fgtHwAccessMod == HW_ACCESS_MODE_F2R) )
    {
      if(dev->fgtHwAccess(dev, regList) != GT_TRUE)
      {
        if(fgtAccessRegs(dev, regList) != GT_TRUE)
        {
          return GT_FAIL;
        }
      }
    }
    else
    {
      if(fgtAccessRegs(dev, regList) != GT_TRUE)
      {
        return GT_FAIL;
      }
    }
  }
  return GT_OK;

}

/*******************************************************************************
* eventSetActive
*
* DESCRIPTION:
*       This routine enables/disables the receive of an hardware driven event.
*
* INPUTS:
*       eventType - the event type. any combination of the folowing: 
*       	GT_STATS_DONE, GT_VTU_PROB, GT_VTU_DONE, GT_ATU_FULL(or GT_ATU_PROB),
*       	GT_ATU_DONE, GT_PHY_INTERRUPT, and GT_EE_INTERRUPT
*
* OUTPUTS:
*       None.
*
* RETURNS:
*       GT_OK   - on success
*       GT_FAIL - on error
*
* COMMENTS:
*       None.
*
* GalTis:
*
*******************************************************************************/
GT_STATUS eventSetActive
(
    IN GT_QD_DEV *dev,
    IN GT_U32 	 eventType
)
{
    GT_STATUS   retVal;   
    GT_U16 	data;
	GT_U16	intMask;

    DBG_INFO(("eventSetActive Called.\n"));

	data = (GT_U16) eventType;

	if (IS_IN_DEV_GROUP(dev,DEV_EXTERNAL_PHY_ONLY))
    {
		intMask = GT_NO_INTERNAL_PHY_INT_MASK;
    }
	else
	{
		intMask = GT_INT_MASK;
	}
	
	if(data & ~intMask)
	{
	    DBG_INFO(("Invalid event type.\n"));
		return GT_FAIL;
	}

    /* Set the IntEn bit.               */
    retVal = hwSetGlobalRegField(dev,QD_REG_GLOBAL_CONTROL,0,7,data);
    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed.\n"));
        return retVal;
    }
    DBG_INFO(("OK.\n"));
    return GT_OK;
}

/*******************************************************************************
* gpavGetIngressMonitor
*
* DESCRIPTION:
*       This routine gets the Ingress Monitor bit in the PAV.
*
* INPUTS:
*       port - the logical port number.
*
* OUTPUTS:
*       mode - the ingress monitor bit in the PAV
*              GT_FALSE: Ingress Monitor enabled
*              GT_TRUE:  Ingress Monitor disabled
*
* RETURNS:
*       GT_OK               - on success
*       GT_FAIL             - on error
*       GT_BAD_PARAM        - on bad parameters
*
* COMMENTS:
*
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gpavGetIngressMonitor
(
    IN GT_QD_DEV *dev,
    IN  GT_LPORT port,
    OUT GT_BOOL  *mode
)
{
    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U16          data;           /* The register's read data.    */
    GT_U8           phyPort;        /* Physical port.               */

    DBG_INFO(("grcGetIngressMonitor Called.\n"));
    if(mode == NULL)
    {
        DBG_INFO(("Failed.\n"));
        return GT_BAD_PARAM;
    }

    phyPort = GT_LPORT_2_PORT(port);

    /* check if device supports this feature */
    if (!IS_IN_DEV_GROUP(dev,DEV_ENABLE_MONITORING))
    {
        DBG_INFO(("GT_NOT_SUPPORTED\n"));
        return GT_NOT_SUPPORTED;
    }

    retVal = hwGetPortRegField(dev,phyPort,QD_REG_PORT_ASSOCIATION,15,1,&data);
    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed.\n"));
        return retVal;
    }

    BIT_2_BOOL(data,*mode);
    DBG_INFO(("OK.\n"));
    return GT_OK;
}

/*******************************************************************************
* gstuDelEntry
*
* DESCRIPTION:
*       Deletes STU entry specified by user.
*
* INPUTS:
*       stuEntry - the STU entry to be deleted 
*
* OUTPUTS:
*       None.
*
* RETURNS:
*       GT_OK           - on success
*       GT_FAIL         - on error
*		GT_NOT_SUPPORTED - if current device does not support this feature.
*
* COMMENTS:
*		Valid SID is 1 ~ 63.
*
*******************************************************************************/
GT_STATUS gstuDelEntry
(
    IN  GT_QD_DEV   	*dev,
    IN  GT_STU_ENTRY 	*stuEntry
)
{
    GT_U8               valid;
    GT_STATUS       	retVal;
    GT_STU_ENTRY    	entry;

    DBG_INFO(("gstuDelEntry Called.\n"));

    /* check if device supports this feature */
	if (!IS_IN_DEV_GROUP(dev,DEV_802_1S_STU))
    {
        DBG_INFO(("GT_NOT_SUPPORTED\n"));
		return GT_NOT_SUPPORTED;
    }
    
    if((stuEntry->sid == 0) || (stuEntry->sid > 0x3F))
	{
        DBG_INFO(("GT_BAD_PARAM\n"));
		return GT_BAD_PARAM;
	}

    entry.sid = stuEntry->sid;
    valid = 0; /* for delete operation */

    retVal = stuOperationPerform(dev,LOAD_PURGE_STU_ENTRY,&valid, &entry);
    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed (stuOperationPerform returned GT_FAIL).\n"));
        return retVal;
    }
    DBG_INFO(("OK.\n"));
    return GT_OK;
}

/*******************************************************************************
* gpavSetIngressMonitor
*
* DESCRIPTION:
*       This routine sets the Ingress Monitor bit in the PAV.
*
* INPUTS:
*       port - the logical port number.
*       mode - the ingress monitor bit in the PAV
*              GT_FALSE: Ingress Monitor enabled 
*              GT_TRUE:  Ingress Monitor disabled 
* OUTPUTS:
*       None.
*
* RETURNS:
*       GT_OK   - on success
*       GT_FAIL - on error
*
* COMMENTS:
*
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gpavSetIngressMonitor
(
    IN GT_QD_DEV *dev,
    IN GT_LPORT  port,
    IN GT_BOOL   mode
)
{
    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U16          data;           /* Data to be set into the      */
                                    /* register.                    */
    GT_U8           phyPort;        /* Physical port.               */

    DBG_INFO(("gpavSetIngressMonitorCalled.\n"));

    phyPort = GT_LPORT_2_PORT(port);
    BOOL_2_BIT(mode,data);

    /* check if device supports this feature */
    if((retVal = IS_VALID_API_CALL(dev,phyPort, DEV_PORT_MONITORING)) != GT_OK ) 
      return retVal;
	
	if (!IS_IN_DEV_GROUP(dev,DEV_ENABLE_MONITORING))
    {
        DBG_INFO(("GT_NOT_SUPPORTED\n"));
		return GT_NOT_SUPPORTED;
    }

    retVal = hwSetPortRegField(dev,phyPort,QD_REG_PORT_ASSOCIATION,15,1,data);
    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed.\n"));
        return retVal;
    }

    DBG_INFO(("OK.\n"));
    return GT_OK;
}

/*******************************************************************************
* gsysGetInitReady
*
* DESCRIPTION:
*       This routine get the InitReady bit. This bit is set to a one when the ATU,
*       the Queue Controller and the Statistics Controller are done with their 
*       initialization and are ready to accept frames.
*
* INPUTS:
*       None.
*
* OUTPUTS:
*       mode - GT_TRUE: switch is ready, GT_FALSE otherwise.
*
* RETURNS:
*       GT_OK           - on success
*       GT_BAD_PARAM    - on bad parameter
*       GT_FAIL         - on error
*
* COMMENTS:
*       None.
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gsysGetInitReady
(
    IN  GT_QD_DEV  *dev,
    OUT GT_BOOL    *mode
)
{
    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U16          data;           /* The register's read data.    */

    DBG_INFO(("gsysGetInitReady Called.\n"));

    /* check if device supports this feature */
	if (!IS_IN_DEV_GROUP(dev,DEV_QD_PLUS|DEV_ENHANCED_FE_SWITCH))
	{
        DBG_INFO(("Not Supported.\n"));
		return GT_NOT_SUPPORTED;
	}

    if(mode == NULL)
    {
        DBG_INFO(("Failed.\n"));
        return GT_BAD_PARAM;
    }

    /* get the bits from hardware */
    retVal = hwGetGlobalRegField(dev,QD_REG_GLOBAL_STATUS,11,1,&data);
    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed.\n"));
        return retVal;
    }

    BIT_2_BOOL(data,*mode);
    DBG_INFO(("OK.\n"));
    return GT_OK;
}

/*******************************************************************************
* gsysGetSW_Mode
*
* DESCRIPTION:
*       This routine get the Switch mode. These two bits returen
*       the current value of the SW_MODE[1:0] pins.
*
* INPUTS:
*       None.
*
* OUTPUTS:
*       mode - GT_TRUE Discard is enabled, GT_FALSE otherwise.
*
* RETURNS:
*       GT_OK           - on success
*       GT_BAD_PARAM    - on bad parameter
*       GT_FAIL         - on error
*
* COMMENTS:
*       None.
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gsysGetSW_Mode
(
    IN  GT_QD_DEV  *dev,
    OUT GT_SW_MODE *mode
)
{
    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U16          data;           /* The register's read data.    */

    DBG_INFO(("gsysGetSW_Mode Called.\n"));

    /* check if device supports this feature */
    if (!(IS_IN_DEV_GROUP(dev,DEV_SWITCH_MODE)) )
    {
        DBG_INFO(("Not Supported.\n"));
        return GT_NOT_SUPPORTED;
    }

    if(mode == NULL)
    {
        DBG_INFO(("Failed.\n"));
        return GT_BAD_PARAM;
    }

    /* get the bits from hardware */
    retVal = hwGetGlobalRegField(dev,QD_REG_GLOBAL_STATUS,12,2,&data);
    if(retVal != GT_OK)
    {
        DBG_INFO(("Failed.\n"));
        return retVal;
    }

    *mode = data;
    DBG_INFO(("OK.\n"));
    return GT_OK;
}

/*******************************************************************************
* gsysSetQoSWeight
*
* DESCRIPTION:
*       Programmable Round Robin Weights.
*        Each port has 4/8 output Queues. Queue 3/7 has the highest priority and 
*        Queue 0 has the lowest priority. When a scheduling mode of port is 
*        configured as Weighted Round Robin queuing mode, the access sequece of the 
*        Queue is 3,2,3,1,3,2,3,0,3,2,3,1,3,2,3 by default.
*        (Queue is 7,6,5,7,1,6,7,4 by default. That is after 6390.)
*        This sequence can be configured with this API.
*
* INPUTS:
*       weight - access sequence of the queue
*
* OUTPUTS:
*       None.
*
* RETURNS:
*       GT_OK      - on success
*       GT_FAIL    - on error
*        GT_NOT_SUPPORTED - if current device does not support this feature.
*
* COMMENTS:
*       None
*
*******************************************************************************/
GT_STATUS gsysSetQoSWeight
(
    IN  GT_QD_DEV         *dev,
    IN  GT_QoS_WEIGHT    *weight
)
{
    GT_STATUS    retVal;         /* Functions return value.      */
    GT_U16        data;
    GT_U32        len, i;
	int length_loc, entry_num;

    DBG_INFO(("gsysSetQoSWeight Called.\n"));

    /* Check if Switch supports this feature. */
    if (!IS_IN_DEV_GROUP(dev,DEV_QoS_WEIGHT))
    {
        DBG_INFO(("GT_NOT_SUPPORTED\n"));
        return GT_NOT_SUPPORTED;
    }

    if (IS_IN_DEV_GROUP(dev,DEV_QoS_WEIGHT_1))
    {
      length_loc = 0x40;
      entry_num = 2;

    }
	else
    {
      length_loc = 0x20;
      entry_num = 4;
    }


    if (weight->len > 128)
    {
        DBG_INFO(("GT_BAD_PARAM\n"));
        return GT_BAD_PARAM;
    }

    gtSemTake(dev,dev->tblRegsSem,OS_WAIT_FOREVER);

    len = weight->len/entry_num;

    /* program QoS Weight Table, 4/2 sequences at a time */

    for(i=0; i<len; i++)
    {
        /* Wait until the QoS Weight Table is ready. */
#ifdef GT_RMGMT_ACCESS
    {
      HW_DEV_REG_ACCESS regAccess;

      regAccess.entries = 2;

      regAccess.rw_reg_list[0].cmd = HW_REG_WAIT_TILL_0;
      regAccess.rw_reg_list[0].addr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS);
      regAccess.rw_reg_list[0].reg = QD_REG_QOS_WEIGHT;
      regAccess.rw_reg_list[0].data = 15;
      regAccess.rw_reg_list[1].cmd = HW_REG_WRITE;
      regAccess.rw_reg_list[1].addr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL2_REG_ACCESS);
      regAccess.rw_reg_list[1].reg = QD_REG_QOS_WEIGHT;
    if (IS_IN_DEV_GROUP(dev,DEV_QoS_WEIGHT_1))
	{
      data =  (GT_U16)((1 << 15) | (i << 8) | 
            (weight->queue[i*2] & 0x7) |
            ((weight->queue[i*2+1] & 0x7) << 4);
	}
	else
	{
      data =  (GT_U16)((1 << 15) | (i << 8) | 
            (weight->queue[i*4] & 0x3) |
            ((weight->queue[i*4+1] & 0x3) << 2) |
            ((weight->queue[i*4+2] & 0x3) << 4) |
//.........这里部分代码省略.........

/*******************************************************************************
* gprtGetSerdesReg
*
* DESCRIPTION:
*       This routine reads Phy Serdes Registers.
*
* INPUTS:
*       port -    The logical port number.
*       regAddr - The register's address.
*
* OUTPUTS:
*       data    - The read register's data.
*
* RETURNS:
*       GT_OK           - on success
*       GT_FAIL         - on error
*
* COMMENTS:
*       None.
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gprtGetSerdesReg
(
    IN  GT_QD_DEV    *dev,
    IN  GT_LPORT     port,
    IN  GT_U32         regAddr,
    OUT GT_U16         *data
)
{
    GT_U8           hwPort, serdesPort;         /* the physical port number     */
	GT_U8           pageNum = _getSerdesPageNumber(dev);
    GT_PHY_INFO        serdesInfo;

    DBG_INFO(("gprtGetSerdesReg Called.\n"));

    if(!IS_IN_DEV_GROUP(dev,DEV_SERDES_UP_PORT))
    {
        return GT_NOT_SUPPORTED;
    }

    /* check if input is logical port number */    
/*    hwPort = GT_LPORT_2_PORT(port);
    GT_GET_SERDES_PORT(dev,&hwPort);
*/
    hwPort = qdLong2Char(port);
	serdesPort = hwPort;
    GT_GET_SERDES_PORT(dev,&serdesPort);
	
    if(hwPort > dev->maxPhyNum)
    {
        /* check if input is physical serdes address */    
        if(dev->validSerdesVec & (1<<port))
        {
            hwPort = (GT_U8)port;
        }
        else
            return GT_NOT_SUPPORTED;
    }
	//printf("===GT_GET_SERDES_PORT serdesPort = %d ,hwPort = %d\r\n",serdesPort,hwPort);

    gtSemTake(dev,dev->phyRegsSem,OS_WAIT_FOREVER);
    /* check if the port is configurable */
    if((serdesInfo.phyId=GT_GET_PHY_ID(dev,hwPort)) == GT_INVALID_PHY)
    {
        gtSemGive(dev,dev->phyRegsSem);
        return GT_NOT_SUPPORTED;
    }

    if(driverFindPhyInformation(dev,hwPort,&serdesInfo) != GT_OK)
    {
        DBG_INFO(("Unknown PHY device.\n"));
        gtSemGive(dev,dev->phyRegsSem);
        return GT_FAIL;
    }


    /* Get Serdes Register. */
    /* Write to Serdes Register */
	//printf("===hwReadPagedPhyReg serdesPort= %d, pageNum = %d,regAddr = %x,serdesInfo.anyPage = %d \r\n",serdesPort,pageNum,(GT_U8)regAddr,serdesInfo.anyPage);
    if(hwReadPagedPhyReg(dev,serdesPort,pageNum,(GT_U8)regAddr,serdesInfo.anyPage,data) != GT_OK)
    {
        DBG_INFO(("Failed.\n"));
        gtSemGive(dev,dev->phyRegsSem);
        return GT_FAIL;
    }

    gtSemGive(dev,dev->phyRegsSem);
    return GT_OK;

}

/*******************************************************************************
* statsCapture
*
* DESCRIPTION:
*       This function is used to capture all counters of a port.
*
* INPUTS:
*       port        - port number
*
* OUTPUTS:
*        None.
*
* RETURNS:
*       GT_OK on success,
*       GT_FAIL otherwise.
*
* COMMENTS:
*        If Semaphore is used, Semaphore should be acquired before this function call.
*******************************************************************************/
static GT_STATUS statsCapture
(
    IN GT_QD_DEV            *dev,
    IN GT_U8             port
)
{
    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U16          data, histoData;/* Data to be set into the      */
                                    /* register.                    */
    GT_U16            portNum;

    if (IS_IN_DEV_GROUP(dev,DEV_RMON_PORT_BITS))
    {
        portNum = (port + 1) << 5;
    }
    else
    {
        portNum = (GT_U16)port;
    }

    /* Get the Histogram mode bit.                */
    retVal = hwReadGlobalReg(dev,QD_REG_STATS_OPERATION,&histoData);
    if(retVal != GT_OK)
    {
        return retVal;
    }

    histoData &= 0xC00;

#ifdef GT_RMGMT_ACCESS
    {
      HW_DEV_REG_ACCESS regAccess;

      regAccess.entries = 1;

      regAccess.rw_reg_list[0].cmd = HW_REG_WAIT_TILL_0;
      regAccess.rw_reg_list[0].addr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS);
      regAccess.rw_reg_list[0].reg = QD_REG_STATS_OPERATION;
      regAccess.rw_reg_list[0].data = 15;
      retVal = hwAccessMultiRegs(dev, &regAccess);
      if(retVal != GT_OK)
      {
        return retVal;
      }
    }
#else
    data = 1;
       while(data == 1)
    {
        retVal = hwGetGlobalRegField(dev,QD_REG_STATS_OPERATION,15,1,&data);
        if(retVal != GT_OK)
           {
               return retVal;
        }
       }
#endif

    data = (1 << 15) | (GT_STATS_CAPTURE_PORT << 12) | portNum | histoData;
    retVal = hwWriteGlobalReg(dev,QD_REG_STATS_OPERATION,data);
    if(retVal != GT_OK)
    {
        return retVal;
    }

    return GT_OK;

}

/*******************************************************************************
* gprtSetPolicy
*
* DESCRIPTION:
*       This routine sets the Policy for ports.
*		Supported Policies are defined as GT_FRAME_POLICY as follows:
*			FRAME_POLICY_NONE    - normal frame switching
*			FRAME_POLICY_MIRROR  - mirror (copy) frame to MirrorDest port
*			FRAME_POLICY_TRAP    - trap(re-direct) frame to the CPUDest port
*			FRAME_POLICY_DISCARD - discard(filter) the frame
*		Supported Policy types are defined as GT_POLICY_TYPE:
*			POLICY_TYPE_DA - DA Policy Mapping
*				DA Policy Mapping occurs when the DA of a frame is contained in 
*				the ATU address database with an Entry State that indicates Policy.
*			POLICY_TYPE_SA - SA Policy Mapping
*				SA Policy Mapping occurs when the SA of a frame is contained in 
*				the ATU address database with an Entry State that indicates Policy.
*			POLICY_TYPE_VTU - VTU Policy Mapping
*				VTU Policy Mapping occurs when the VID of a frame is contained in
*				the VTU database with the VidPolicy is enabled.
*			POLICY_TYPE_ETYPE - EtherType Policy Mapping
*				EType Policy Mapping occurs when the EtherType of a frame matches
*				the PortEType (see gprtSetPortEType API)
*			POLICY_TYPE_PPPoE - PPPoE Policy Mapping
*				PPPoE Policy Mapping occurs when the EtherType of a frame matches 0x8863
*			POLICY_TYPE_VBAS - VBAS Policy Mapping
*				VBAS Policy Mapping occurs when the EtherType of a frame matches 0x8200
*			POLICY_TYPE_OPT82 - DHCP Option 82 Policy Mapping
*				DHCP Option 82 Policy Mapping occurs when the ingressing frame is an
*				IPv4 UDP with a UDP Destination port = 0x0043 or 0x0044, or an
*				IPv6 UDP with a UDP Destination port = 0x0223 or 0x0222
*			POLICY_TYPE_UDP - UDP Policy Mapping
*				UDP Policy Mapping occurs when the ingressing frame is
*				a Broadcast IPv4 UDP or a Multicast IPv6 UDP.
*
* INPUTS:
*       port	- logical port number.
*       type 	- policy type (GT_POLICY_TYPE)
*       policy 	- policy (GT_FRAME_POLICY)
*
* OUTPUTS:
*       None.
*
* RETURNS:
*       GT_OK            - on success
*       GT_FAIL          - on error
*       GT_BAD_PARAM     - on bad parameters
*		GT_NOT_SUPPORTED - if current device does not support this feature.
*
* COMMENTS: 
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gprtSetPolicy
(
    IN  GT_QD_DEV 	*dev,
    IN  GT_LPORT 	port,
    IN  GT_POLICY_TYPE	type,
	IN	GT_FRAME_POLICY	policy
)
{

    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U8           hwPort;         /* Physical port.               */
    GT_U8	    	offset;

    DBG_INFO(("gprtSetPolicy Called.\n"));

    /* translate LPORT to hardware port */
    hwPort = GT_LPORT_2_PORT(port);
    
    /* check if device supports this feature */
	if (!IS_IN_DEV_GROUP(dev,DEV_POLICY))
	{
        DBG_INFO(("GT_NOT_SUPPORTED\n"));
		return GT_NOT_SUPPORTED;
	}

	switch (policy)
	{
		case FRAME_POLICY_NONE:
		case FRAME_POLICY_MIRROR:
		case FRAME_POLICY_TRAP:
		case FRAME_POLICY_DISCARD:
			break;
		default:
	        DBG_INFO(("Bad Policy\n"));
			return GT_BAD_PARAM;
	}
		
	switch (type)
	{
		case POLICY_TYPE_DA:
			offset = 14;
			break;
		case POLICY_TYPE_SA:
			offset = 12;
			break;
		case POLICY_TYPE_VTU:
//.........这里部分代码省略.........

//.........这里部分代码省略.........
    }

    /* Initialize the PHY Device Register Access semaphore.    */
    if((dev->phyRegsSem = gtSemCreate(dev,GT_SEM_FULL)) == 0)
    {
        DBG_INFO(("semCreate Failed.\n"));
        qdUnloadDriver(dev);
        return GT_FAIL;
    }

    /* Initialize the ports states to forwarding mode. */
    if(cfg->initPorts == GT_TRUE)
    {
		for (port=0; port<dev->numOfPorts; port++)
		{
			if((retVal = gstpSetPortState(dev,port,GT_PORT_FORWARDING)) != GT_OK)
   			{
	    	    DBG_INFO(("Failed.\n"));
				qdUnloadDriver(dev);
   		    	return retVal;
	    	}
		}
    }

    if(cfg->skipInitSetup == GT_SKIP_INIT_SETUP)
	{
	    dev->devEnabled = 1;
    	dev->devNum = cfg->devNum;

	    DBG_INFO(("OK.\n"));
    	return GT_OK;
	}

	if(IS_IN_DEV_GROUP(dev,DEV_ENHANCED_CPU_PORT))
	{
		if((retVal = gsysSetRsvd2CpuEnables(dev,0)) != GT_OK)
		{
	        DBG_INFO(("gsysGetRsvd2CpuEnables failed.\n"));
			qdUnloadDriver(dev);
			return retVal;
		}

		if((retVal = gsysSetRsvd2Cpu(dev,GT_FALSE)) != GT_OK)
		{
	        DBG_INFO(("gsysSetRsvd2Cpu failed.\n"));
			qdUnloadDriver(dev);
			return retVal;
		}
	}

	if (IS_IN_DEV_GROUP(dev,DEV_CPU_DEST_PER_PORT))
	{
		for (port=0; port<dev->numOfPorts; port++)
		{
			retVal = gprtSetCPUPort(dev,port,dev->cpuPortNum);
		    if(retVal != GT_OK)
    		{
	    	    DBG_INFO(("Failed.\n"));
				qdUnloadDriver(dev);
	   	    	return retVal;
		    }
		}
	}

	if(IS_IN_DEV_GROUP(dev,DEV_CPU_PORT))
	{

//.........这里部分代码省略.........
				phyInfo->vctType = GT_PHY_VCT_TYPE2;
				phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE1;
				if ((phyId & PHY_REV_MASK) < 4)
					phyInfo->dteType = GT_PHY_DTE_TYPE3;	/* Need workaround */
				else
					phyInfo->dteType = GT_PHY_DTE_TYPE2;

				phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE1;
				phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1;
				phyInfo->lineLoopType = 0;
				phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0;
				phyInfo->pageType = GT_PHY_PAGE_DIS_AUTO1;

				break;

		case DEV_E1149:
				phyInfo->anyPage = 0x2040FFFF;
				phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE|
								GT_PHY_EX_CABLE_STATUS|
								GT_PHY_GIGABIT|
								GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP|
								GT_PHY_PKT_GENERATOR;
				phyInfo->vctType = GT_PHY_VCT_TYPE4;
				phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE3;
				phyInfo->dteType = GT_PHY_DTE_TYPE4;
				phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2;
				phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1;
				phyInfo->lineLoopType = 0;
				phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0;
				phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK;
				break;

		case DEV_G15LV:
				if (IS_IN_DEV_GROUP(dev,DEV_88E6108))
				{
					phyInfo->anyPage = 0x2040FFFF;
					phyInfo->flag = GT_PHY_VCT_CAPABLE|GT_PHY_DTE_CAPABLE|
									GT_PHY_EX_CABLE_STATUS|
									GT_PHY_GIGABIT|
									GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP|
									GT_PHY_PKT_GENERATOR;
					phyInfo->vctType = GT_PHY_VCT_TYPE4;
					phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE3;
					phyInfo->dteType = GT_PHY_DTE_TYPE4;
					phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2;
					phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1;
					phyInfo->lineLoopType = 0;
					phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0;
					phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK;
				}
				else /* 88E6165 family */
				{
					phyInfo->anyPage = 0x2040FFFF;
					phyInfo->flag = GT_PHY_ADV_VCT_CAPABLE|GT_PHY_DTE_CAPABLE|
									GT_PHY_EX_CABLE_STATUS|
									GT_PHY_GIGABIT|
									GT_PHY_MAC_IF_LOOP|GT_PHY_LINE_LOOP|GT_PHY_EXTERNAL_LOOP|
									GT_PHY_PKT_GENERATOR;
					phyInfo->vctType = GT_PHY_ADV_VCT_TYPE2;
					phyInfo->exStatusType = GT_PHY_EX_STATUS_TYPE6;
					phyInfo->dteType = GT_PHY_DTE_TYPE4;
					phyInfo->pktGenType = GT_PHY_PKTGEN_TYPE2;
					phyInfo->macIfLoopType = GT_PHY_LOOPBACK_TYPE1;
					phyInfo->lineLoopType = 0;
					phyInfo->exLoopType = GT_PHY_EX_LB_TYPE0;
					phyInfo->pageType = GT_PHY_PAGE_WRITE_BACK;

//.........这里部分代码省略.........
            }
        }
    }

    dev->use_mad = GT_FALSE;
#ifdef GT_USE_MAD  
	{
	  int portPhyAddr=0;
	  unsigned int validPhyVec = dev->validPhyVec;
	  while((validPhyVec&1)==0)
	  {
        validPhyVec >>= 1;
	    portPhyAddr++;
	  }
      DBG_INFO(("@@@@@@@@@@ qd_madInit\n"));
      if((retVal = qd_madInit(dev, portPhyAddr)) != GT_OK)
      {
        DBG_INFO(("Initialize MAD failed.\n"));
        qdUnloadDriver(dev);
        return retVal;
      }
	}
#endif

    if(cfg->skipInitSetup == GT_SKIP_INIT_SETUP)
    {
        dev->devEnabled = 1;
        dev->devNum = cfg->devNum;

        DBG_INFO(("OK.\n"));
        return GT_OK;
    }

    if(IS_IN_DEV_GROUP(dev,DEV_ENHANCED_CPU_PORT))
    {
        if((retVal = gsysSetRsvd2CpuEnables(dev,0)) != GT_OK)
        {
            DBG_INFO(("gsysGetRsvd2CpuEnables failed.\n"));
            qdUnloadDriver(dev);
            return retVal;
        }

        if((retVal = gsysSetRsvd2Cpu(dev,GT_FALSE)) != GT_OK)
        {
            DBG_INFO(("gsysSetRsvd2Cpu failed.\n"));
            qdUnloadDriver(dev);
            return retVal;
        }
    }

    if (IS_IN_DEV_GROUP(dev,DEV_CPU_DEST_PER_PORT))
    {
        for (port=0; port<dev->numOfPorts; port++)
        {
            retVal = gprtSetCPUPort(dev,port,dev->cpuPortNum);
            if(retVal != GT_OK)
            {
                DBG_INFO(("Failed.\n"));
                qdUnloadDriver(dev);
                   return retVal;
            }
        }
    }

    if(IS_IN_DEV_GROUP(dev,DEV_CPU_PORT))
    {

/*******************************************************************************
* gstpSetMode
*
* DESCRIPTION:
*       This routine Enable the Spanning tree.
*
* INPUTS:
*       en - GT_TRUE for enable, GT_FALSE for disable.
*
* OUTPUTS:
*       None.
*
* RETURNS:
*       GT_OK   - on success
*       GT_FAIL - on error
*
* COMMENTS:
*       when enabled, this function sets all port to blocking state, and inserts
*       the BPDU MAC into the ATU to be captured to CPU, on disable all port are
*       being modified to be in forwarding state.
*
* GalTis:
*
*******************************************************************************/
GT_STATUS gstpSetMode
(
    IN GT_QD_DEV *dev,
    IN GT_BOOL  en
)
{
    GT_STATUS       retVal = GT_OK; /* Functions return value.      */
    GT_ATU_ENTRY        atuEntry;   /* The ATU entry data to be set */
    GT_U32          i, dbNum;

    DBG_INFO(("gstpSetMode Called.\n"));
    if(dev->deviceId == GT_88E6051)
    {
        DBG_INFO(("Failed.\n"));
        return GT_FAIL;
    }

    if((en == GT_TRUE) && (dev->stpMode == 1))
    {
        DBG_INFO(("OK.\n"));
        return GT_OK;
    }

	switch(dev->deviceId)
	{
		case GT_88E6051:
		case GT_88E6052:
			dbNum = 1;
			break;
		case GT_FF_HG:
		case GT_FF_EG:
		case GT_88E6021:
		case GT_88E6060:
		case GT_88E6031:
		case GT_88E6061:
		case GT_88E6063:
		case GT_FH_VPN:
		case GT_88E6083:
		case GT_88E6153:
		case GT_88E6181:
		case GT_88E6183:
		case GT_88E6093:
			dbNum = 16;
			break;
		case GT_88E6035:
		case GT_88E6055:
		case GT_88E6065:
			dbNum = 64;
			break;
		default:
			if (!IS_IN_DEV_GROUP(dev,DEV_ENHANCED_MULTICAST))
			{
				dbNum = 64;
			}
			else
			{
				dbNum = 0;
				retVal = enhancedBPDUSet(dev,en);
			}
			break;
	}

	for (i=0; i<dbNum; i++)
	{
	    /* Set the Atu entry parameters.    */
    	atuEntry.macAddr.arEther[0] = 0x01;
	    atuEntry.macAddr.arEther[1] = 0x80;
    	atuEntry.macAddr.arEther[2] = 0xC2;
	    atuEntry.macAddr.arEther[3] = 0x00;
    	atuEntry.macAddr.arEther[4] = 0x00;
	    atuEntry.macAddr.arEther[5] = 0x00;
    	atuEntry.portVec = GT_LPORTVEC_2_PORTVEC((1<<dev->cpuPortNum));
		if(IS_IN_DEV_GROUP(dev,DEV_ATU_EXT_PRI))
		{
			if(IS_IN_DEV_GROUP(dev,DEV_FQPRI_IN_TABLE))
			{
//.........这里部分代码省略.........

//.........这里部分代码省略.........
        return GT_FAIL;
    }

    /* Initialize the STATS semaphore.    */
    if((dev->statsRegsSem = gtSemCreate(dev,GT_SEM_FULL)) == 0)
    {
        DBG_INFO(("semCreate Failed.\n"));
		qdUnloadDriver(dev);
        return GT_FAIL;
    }

    /* Initialize the PIRL semaphore.    */
    if((dev->pirlRegsSem = gtSemCreate(dev,GT_SEM_FULL)) == 0)
    {
        DBG_INFO(("semCreate Failed.\n"));
		qdUnloadDriver(dev);
        return GT_FAIL;
    }

    /* Initialize the ports states to forwarding mode. */
    if(cfg->initPorts == GT_TRUE)
    {
		for (port=0; port<dev->numOfPorts; port++)
		{
			if((retVal = gstpSetPortState(dev,port,GT_PORT_FORWARDING)) != GT_OK)
   			{
	    	    DBG_INFO(("Failed.\n"));
				qdUnloadDriver(dev);
   		    	return retVal;
	    	}
		}
    }

	if(IS_IN_DEV_GROUP(dev,DEV_ENHANCED_CPU_PORT))
	{
		if((retVal = gsysSetRsvd2CpuEnables(dev,0)) != GT_OK)
		{
	        DBG_INFO(("gsysGetRsvd2CpuEnables failed.\n"));
			qdUnloadDriver(dev);
			return retVal;
		}

		if((retVal = gsysSetRsvd2Cpu(dev,GT_FALSE)) != GT_OK)
		{
	        DBG_INFO(("gsysSetRsvd2Cpu failed.\n"));
			qdUnloadDriver(dev);
			return retVal;
		}
	}

	if (IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH))
	{
		for (port=0; port<dev->numOfPorts; port++)
		{
			retVal = gprtSetCPUPort(dev,port,dev->cpuPortNum);
		    if((retVal != GT_OK) && (retVal != GT_NOT_SUPPORTED))
    		{
	    	    DBG_INFO(("Failed.\n"));
				qdUnloadDriver(dev);
	   	    	return retVal;
		    }
		}
	}

	if(IS_IN_DEV_GROUP(dev,DEV_CPU_PORT))
	{

static GT_STATUS statsOperationPerform
(
    IN   GT_QD_DEV            *dev,
    IN   GT_STATS_OPERATION   statsOp,
    IN   GT_U8                port,
    IN   GT_STATS_COUNTERS    counter,
    OUT  GT_VOID              *statsData
)
{
    GT_STATUS       retVal;         /* Functions return value.      */
    GT_U16          data,histoData; /* Data to be set into the      */
                                    /* register.                    */
    GT_U32 statsCounter;
    GT_U32 lastCounter;
    GT_U16            portNum;

    gtSemTake(dev,dev->statsRegsSem,OS_WAIT_FOREVER);

    if (!((IS_IN_DEV_GROUP(dev,DEV_GIGABIT_SWITCH)) ||
        (IS_IN_DEV_GROUP(dev,DEV_RMON_REALTIME_SUPPORT))))
    {
      if (IS_IN_DEV_GROUP(dev,DEV_MELODY_SWITCH))
        lastCounter = (GT_U32)STATS2_Late;
      else
        lastCounter = (GT_U32)STATS_OutDiscards;
    }
    else
    {
        lastCounter = (GT_U32)STATS2_Late;
    }

    if (IS_IN_DEV_GROUP(dev,DEV_RMON_PORT_BITS))
    {
        portNum = (port + 1) << 5;
    }
    else
    {
        portNum = (GT_U16)port;
    }

    /* Wait until the stats in ready. */
#ifdef GT_RMGMT_ACCESS
    {
      HW_DEV_REG_ACCESS regAccess;

      regAccess.entries = 2;

      regAccess.rw_reg_list[0].cmd = HW_REG_WAIT_TILL_0;
      regAccess.rw_reg_list[0].addr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS);
      regAccess.rw_reg_list[0].reg = QD_REG_STATS_OPERATION;
      regAccess.rw_reg_list[0].data = 15;
      regAccess.rw_reg_list[1].cmd = HW_REG_READ;
      regAccess.rw_reg_list[1].addr = CALC_SMI_DEV_ADDR(dev, 0, GLOBAL_REG_ACCESS);
      regAccess.rw_reg_list[1].reg = QD_REG_STATS_OPERATION;
      regAccess.rw_reg_list[1].data = 0;
      retVal = hwAccessMultiRegs(dev, &regAccess);
      if(retVal != GT_OK)
      {
        gtSemGive(dev,dev->statsRegsSem);
        return retVal;
      }
      histoData = qdLong2Short(regAccess.rw_reg_list[1].data);
    }
#else
    data = 1;
    while(data == 1)
    {
        retVal = hwGetGlobalRegField(dev,QD_REG_STATS_OPERATION,15,1,&data);
        if(retVal != GT_OK)
        {
            gtSemGive(dev,dev->statsRegsSem);
            return retVal;
        }
    }

    /* Get the Histogram mode bit.                */
    retVal = hwReadGlobalReg(dev,QD_REG_STATS_OPERATION,&histoData);
    if(retVal != GT_OK)
    {
        gtSemGive(dev,dev->statsRegsSem);
        return retVal;
    }

#endif
    histoData &= 0xC00;

    /* Set the STAT Operation register */
    switch (statsOp)
    {
        case STATS_FLUSH_ALL:
            data = (1 << 15) | (GT_STATS_FLUSH_ALL << 12) | histoData;
            retVal = hwWriteGlobalReg(dev,QD_REG_STATS_OPERATION,data);
            gtSemGive(dev,dev->statsRegsSem);
            return retVal;

        case STATS_FLUSH_PORT:
            data = (1 << 15) | (GT_STATS_FLUSH_PORT << 12) | portNum | histoData;
            retVal = hwWriteGlobalReg(dev,QD_REG_STATS_OPERATION,data);
            gtSemGive(dev,dev->statsRegsSem);
            return retVal;
//.........这里部分代码省略.........