static void
I830ShowCursor(ScrnInfoPtr pScrn)
{
   I830Ptr pI830 = I830PTR(pScrn);
   CARD32 temp;

   DPRINTF(PFX, "I830ShowCursor\n");
   DPRINTF(PFX,
	   "Value of CursorMem.Physical is %x, "
	   " Value of CursorMem.Start is %x ",
	   pI830->CursorMem.Physical, pI830->CursorMem.Start);

   pI830->cursorOn = TRUE;
   if (IS_MOBILE(pI830)) {
      temp = INREG(CURSOR_A_CONTROL);
      temp &= ~CURSOR_MODE;
      temp |= CURSOR_MODE_64_4C_AX;
      /* Need to set mode, then address. */
      OUTREG(CURSOR_A_CONTROL, temp);
      OUTREG(CURSOR_A_BASE, pI830->CursorMem.Physical);
   } else {
      temp = INREG(CURSOR_CONTROL);
      temp |= CURSOR_ENABLE;
      OUTREG(CURSOR_CONTROL, temp);
   }
}

static void
WaitForIdle()
{
    // Wait for the graphics engine to be completely idle.  That is, the FIFO
    // has drained, the Pixel Cache is flushed, and the engine is idle.  This
    // is a standard "sync" function that will make the hardware "quiescent".

    WaitForFifo(64);

    while (true) {
        for (uint32 i = 0; i < R128_TIMEOUT; i++) {
            if ( ! (INREG(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
                Rage128_EngineFlush();
                return ;
            }
        }

        TRACE("Idle timed out: %d entries, stat=0x%08x, probe=0x%08x\n",
              INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK,
              INREG(R128_GUI_STAT),
              INREG(R128_GUI_PROBE));
        TRACE("Idle timed out, resetting engine...\n");

        Rage128_EngineReset();
    }
}

static void
i830_dvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
		  DisplayModePtr adjusted_mode)
{
    ScrnInfoPtr		    scrn = output->scrn;
    intel_screen_private    *intel = intel_get_screen_private(scrn);
    xf86CrtcPtr	    crtc = output->crtc;
    I830CrtcPrivatePtr	    intel_crtc = crtc->driver_private;
    I830OutputPrivatePtr    intel_output = output->driver_private;
    struct _I830DVODriver   *drv = intel_output->i2c_drv;
    int			    pipe = intel_crtc->pipe;
    uint32_t		    dvo;
    unsigned int	    dvo_reg = drv->dvo_reg, dvo_srcdim_reg;
    int			    dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;

    switch (dvo_reg) {
    case DVOA:
    default:
	dvo_srcdim_reg = DVOA_SRCDIM;
	break;
    case DVOB:
	dvo_srcdim_reg = DVOB_SRCDIM;
	break;
    case DVOC:
	dvo_srcdim_reg = DVOC_SRCDIM;
	break;
    }

    intel_output->i2c_drv->vid_rec->mode_set(intel_output->i2c_drv->dev_priv,
					     mode, adjusted_mode);

    /* Save the data order, since I don't know what it should be set to. */
    dvo = INREG(dvo_reg) & (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
    dvo |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | DVO_BLANK_ACTIVE_HIGH;

    if (pipe == 1)
	dvo |= DVO_PIPE_B_SELECT;
    dvo |= DVO_PIPE_STALL;
    if (adjusted_mode->Flags & V_PHSYNC)
	dvo |= DVO_HSYNC_ACTIVE_HIGH;
    if (adjusted_mode->Flags & V_PVSYNC)
	dvo |= DVO_VSYNC_ACTIVE_HIGH;

    OUTREG(dpll_reg, INREG(dpll_reg) | DPLL_DVO_HIGH_SPEED);

    /*OUTREG(DVOB_SRCDIM,
      (adjusted_mode->HDisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
      (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
    OUTREG(dvo_srcdim_reg,
	   (adjusted_mode->HDisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	   (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));
    /*OUTREG(DVOB, dvo);*/
    OUTREG(dvo_reg, dvo);
}

void
I810RefreshRing(ScrnInfoPtr pScrn)
{
   I810Ptr pI810 = I810PTR(pScrn);

   pI810->LpRing.head = INREG(LP_RING + RING_HEAD) & HEAD_ADDR;
   pI810->LpRing.tail = INREG(LP_RING + RING_TAIL);
   pI810->LpRing.space = pI810->LpRing.head - (pI810->LpRing.tail + 8);
   if (pI810->LpRing.space < 0)
      pI810->LpRing.space += pI810->LpRing.mem.Size;

   pI810->AccelInfoRec->NeedToSync = TRUE;
}

static void radeon_gpio_setsda(void* data, int state)
{
	struct radeon_i2c_chan 	*chan = data;
	struct radeonfb_info	*rinfo = chan->rinfo;
	u32			val;
	
	val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN);
	if (!state)
		val |= VGA_DDC_DATA_OUT_EN;

	OUTREG(chan->ddc_reg, val);
	(void)INREG(chan->ddc_reg);
}

static status_t RADEON_VIPFifoIdle(device_info *di, uint8 channel)
{
	vuint8 *regs = di->regs;
	uint32 timeout;

	timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
	if((timeout & 0x0000000f) & channel) /* lockup ?? */
	{
		OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
		return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
	}
	return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK ;
}

int main(int argc, char **argv)
{
    pid_t child;
    uint64_t ring_idle = 0, ring_time = 0;
    struct timeval start, end;
    static struct rusage rusage;
    int status;

    intel_mmio_use_pci_bar(intel_get_pci_device());

    if (argc == 1) {
        fprintf(stderr, "usage: %s cmd [args...]\n", argv[0]);
        return 1;
    }

    signal(SIGCHLD, sighandler);
    signal(SIGINT, SIG_IGN);
    signal(SIGQUIT, SIG_IGN);

    gettimeofday(&start, NULL);
    child = spawn(argv+1);
    if (child < 0)
        return 127;

    while (!goddo) {
        uint32_t ring_head, ring_tail;

        ring_head = INREG(LP_RING + RING_HEAD) & HEAD_ADDR;
        ring_tail = INREG(LP_RING + RING_TAIL) & TAIL_ADDR;

        if (ring_tail == ring_head)
            ring_idle++;
        ring_time++;

        usleep(1000000 / SAMPLES_PER_SEC);
    }
    gettimeofday(&end, NULL);
    timersub(&end, &start, &end);

    waitpid(child, &status, 0);

    getrusage(RUSAGE_CHILDREN, &rusage);
    printf("user: %ld.%06lds, sys: %ld.%06lds, elapsed: %ld.%06lds, CPU: %.1f%%, GPU: %.1f%%\n",
           rusage.ru_utime.tv_sec, rusage.ru_utime.tv_usec,
           rusage.ru_stime.tv_sec, rusage.ru_stime.tv_usec,
           end.tv_sec, end.tv_usec,
           100*(rusage.ru_utime.tv_sec + 1e-6*rusage.ru_utime.tv_usec + rusage.ru_stime.tv_sec + 1e-6*rusage.ru_stime.tv_usec) / (end.tv_sec + 1e-6*end.tv_usec),
           100 - ring_idle * 100. / ring_time);

    return WEXITSTATUS(status);
}

// read data from VIP
// CP lock must be hold
static bool do_VIPRead( 
	device_info *di, uint channel, uint address, uint32 *data )
{
	vuint8 *regs = di->regs;

	Radeon_WaitForFifo( di, 2 );
	// the 0x2000 is the nameless "register-read" flag
	OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 );
	
	if( !Radeon_VIPWaitForIdle( di ))
		return false;

	// enable VIP register cycle reads
	Radeon_WaitForFifo( di, 2 );
	OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0, 
		~RADEON_VIPH_TIMEOUT_STAT_AK_MASK & ~RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS );
	//Radeon_WaitForIdle( di, false, false );
	
	// this read starts a register cycle; the returned value has no meaning
	INREG( regs, RADEON_VIPH_REG_DATA );
	
	if( !Radeon_VIPWaitForIdle( di ))
		return false;
		
	//Radeon_WaitForIdle( di, false, false );
	
	// register cycle is done, so disable any further cycle
	Radeon_WaitForFifo( di, 2 );
	OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS, 
		~RADEON_VIPH_TIMEOUT_STAT_AK_MASK & ~RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS );
	//Radeon_WaitForIdle( di, false, false );
	
	// get the data
	*data = INREG( regs, RADEON_VIPH_REG_DATA );
	
	//SHOW_FLOW( 4, "channel=%d, address=%x, data=%lx", channel, address, *data );

	if( !Radeon_VIPWaitForIdle( di ))
		return false;

	// disable register cycle again (according to sample code)
	// IMHO, this is not necessary as it has been done before
	Radeon_WaitForFifo( di, 2 );
	OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS, 
		~RADEON_VIPH_TIMEOUT_STAT_AK_MASK & ~RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS );

	return true;
}

// reset VIP
void Radeon_VIPReset( 
	device_info *di, bool lock )
{
	vuint8 *regs = di->regs;

	if( lock )
		ACQUIRE_BEN( di->si->cp.lock );

	Radeon_WaitForFifo( di, 5 ); // Radeon_WaitForIdle( di, false, false );
	switch(di->asic){
	    case rt_r200:
	    case rt_rs200:
	    case rt_rv200:
	    case rt_rs100:
		case rt_rv100:
		case rt_r100:
	    OUTREG( regs, RADEON_VIPH_CONTROL, 4 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
			RADEON_VIPH_CONTROL_VIPH_DMA_MODE |	RADEON_VIPH_CONTROL_VIPH_EN ); // slowest, timeout in 16 phases
	    OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | 
	    	RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
	    OUTREG( regs, RADEON_VIPH_DV_LAT, 
	    		0xff |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT)); // set timeslice
	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x151);
	    OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
	default:
		    OUTREG( regs, RADEON_VIPH_CONTROL, 9 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
				RADEON_VIPH_CONTROL_VIPH_DMA_MODE |	RADEON_VIPH_CONTROL_VIPH_EN ); // slowest, timeout in 16 phases
	    OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | 
		    	RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
	    OUTREG( regs, RADEON_VIPH_DV_LAT, 
			    0xff |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT) |
				(4 << RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT)); // set timeslice
	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x0);
	    OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
	    break;

	} 
		
	if( lock )
		RELEASE_BEN( di->si->cp.lock );
}

int main(int argc, char **argv)
{
	I830Rec i830;
	I830Ptr pI830 = &i830;
	int swf14, acpi_lid;

	intel_i830rec_init(pI830);

	while (1) {
		swf14 = INREG(SWF14);

		printf("Intel LVDS Lid status:\n");
		printf("\tSWF14(0x%x) : %s\n", swf14,
		       swf14 & SWF14_LID_SWITCH_EN ? "close" : "open");

		acpi_lid = i830_lvds_acpi_lid_state();
		switch (acpi_lid) {
		case LID_UNKNOWN:
			printf("\tACPI Lid state : unknown\n");
			break;
		case LID_OPEN:
			printf("\tACPI Lid state : open\n");
			break;
		case LID_CLOSE:
			printf("\tACPI Lid state : close\n");
			break;
		}
		sleep(2);
	}
	return 0;
}

void
I810RefreshRing(ScrnInfoPtr pScrn)
{
   I810Ptr pI810 = I810PTR(pScrn);

   pI810->LpRing->head = INREG(LP_RING + RING_HEAD) & HEAD_ADDR;
   pI810->LpRing->tail = INREG(LP_RING + RING_TAIL);
   pI810->LpRing->space = pI810->LpRing->head - (pI810->LpRing->tail + 8);
   if (pI810->LpRing->space < 0)
      pI810->LpRing->space += pI810->LpRing->mem.Size;

#if HAVE_XAA_H
   if (pI810->AccelInfoRec)
      pI810->AccelInfoRec->NeedToSync = TRUE;
#endif
}

static bool lpsp_is_enabled(int drm_fd)
{
	uint32_t val;

	val = INREG(HSW_PWR_WELL_CTL2);
	return !(val & HSW_PWR_WELL_STATE_ENABLED);
}

// cleanup PCI GART
void Radeon_CleanupPCIGART( device_info *di )
{
	vuint8 *regs = di->regs;

	SHOW_FLOW0( 3, "" );

	// perhaps we should wait for FIFO space before messing around with registers, but
	// 1. I don't want to add all the sync stuff to the kernel driver
	// 2. I doubt that these regs are buffered by FIFO
	// but still: in worst case CP has written some commands to register FIFO,
	// which can do any kind of nasty things

	// disable CP BM
	OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
	// read-back for flushing
	INREG( regs, RADEON_CP_CSQ_CNTL );

	// disable bus mastering
	OUTREGP( regs, RADEON_BUS_CNTL, RADEON_BUS_MASTER_DIS, ~RADEON_BUS_MASTER_DIS );
	// disable PCI GART
	OUTREGP( regs, RADEON_AIC_CNTL, 0, ~RADEON_PCIGART_TRANSLATE_EN );

	destroyGATT( &di->pci_gart );
	destroyGARTBuffer( &di->pci_gart );
}

static void R128DRIIrqInit(const DRIDriverContext *ctx)
{
   R128InfoPtr info = ctx->driverPrivate;
   unsigned char *R128MMIO = ctx->MMIOAddress;
   
   if (!info->irq) {
       info->irq = drmGetInterruptFromBusID(
	   ctx->drmFD,
	   ctx->pciBus,
	   ctx->pciDevice,
	   ctx->pciFunc);

      if((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
	 fprintf(stderr,
		    "[drm] failure adding irq handler, "
		    "there is a device already using that irq\n"
		    "[drm] falling back to irq-free operation\n");
	 info->irq = 0;
      } else {
          info->gen_int_cntl = INREG( R128_GEN_INT_CNTL );
      }
   }

   if (info->irq)
      fprintf(stderr,
		 "[drm] dma control initialized, using IRQ %d\n",
		 info->irq);
}

int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn,
			       u8 **out_edid)
{
	u8 *edid;

	edid = fb_ddc_read(&rinfo->i2c[conn-1].adapter);

	if (out_edid)
		*out_edid = edid;
	if (!edid) {
		pr_debug("radeonfb: I2C (port %d) ... not found\n", conn);
		return MT_NONE;
	}
	if (edid[0x14] & 0x80) {
		/* Fix detection using BIOS tables */
		if (rinfo->is_mobility /*&& conn == ddc_dvi*/ &&
		    (INREG(LVDS_GEN_CNTL) & LVDS_ON)) {
			pr_debug("radeonfb: I2C (port %d) ... found LVDS panel\n", conn);
			return MT_LCD;
		} else {
			pr_debug("radeonfb: I2C (port %d) ... found TMDS panel\n", conn);
			return MT_DFP;
		}
	}
	pr_debug("radeonfb: I2C (port %d) ... found CRT display\n", conn);
	return MT_CRT;
}

// copy from graphics memory to other memory via DMA
// 	src		- offset in graphics mem
//	target	- target address
//	size	- number of bytes to copy
//	lock_mem - true, if memory is not locked
//	contiguous - true, if memory is physically contiguous (implies lock_mem=false)
status_t Radeon_DMACopy( 
	device_info *di, uint32 src, char *target, size_t size, bool lock_mem, bool contiguous )
{
	status_t res;
	
	/*SHOW_FLOW( 0, "src=%ld, target=%p, size=%ld, lock_mem=%d, contiguous=%d",
		src, target, size, lock_mem, contiguous );*/
	
	res =  Radeon_PrepareDMA( di, src, target, size, lock_mem, contiguous );
	if( res != B_OK )
		return res;
		
	//SHOW_FLOW0( 0, "2" );

	OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start +
		di->dma_desc_offset );
		
	res = acquire_sem_etc( di->dma_sem, 1, B_RELATIVE_TIMEOUT, 1000000 );
	
	// be sure that transmission is really finished
	while( (INREG( di->regs, RADEON_DMA_VID_STATUS ) & RADEON_DMA_STATUS_ACTIVE) != 0 ) {
		SHOW_FLOW0( 0, "DMA transmission still active" );
		snooze( 1000 );
	}
		
	Radeon_FinishDMA( di, src, target, size, lock_mem, contiguous );
	
	//SHOW_FLOW0( 0, "3" );
	
	return res;
}

static void
i830_dvo_save(xf86OutputPtr output)
{
    ScrnInfoPtr		    scrn = output->scrn;
    intel_screen_private    *intel = intel_get_screen_private(scrn);
    I830OutputPrivatePtr    intel_output = output->driver_private;
    void *		    dev_priv = intel_output->i2c_drv->dev_priv;

    /* Each output should probably just save the registers it touches, but for
     * now, use more overkill.
     */
    intel->saveDVOA = INREG(DVOA);
    intel->saveDVOB = INREG(DVOB);
    intel->saveDVOC = INREG(DVOC);

    (*intel_output->i2c_drv->vid_rec->save)(dev_priv);
}

static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
{
	u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl, fp_gen_cntl, fp2_gen_cntl;
 
	crtcGenCntl  = INREG( CRTC_GEN_CNTL);
	crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);

	memRefreshCntl 	= INREG( MEM_REFRESH_CNTL);
	crtc_more_cntl 	= INREG( CRTC_MORE_CNTL);
	fp_gen_cntl 	= INREG( FP_GEN_CNTL);
	fp2_gen_cntl 	= INREG( FP2_GEN_CNTL);
 

	OUTREG( CRTC_MORE_CNTL, 	0);
	OUTREG( FP_GEN_CNTL, 	0);
	OUTREG( FP2_GEN_CNTL, 	0);
 
	OUTREG( CRTC_GEN_CNTL,  (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
	OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
  
	/* Disable refresh */
	OUTREG( MEM_REFRESH_CNTL, memRefreshCntl | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
 
	/* Reset memory */
	OUTREG( MEM_SDRAM_MODE_REG,
		INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init  Not Complete

	/* DLL */
	radeon_pm_enable_dll(rinfo);

	// MLCK /YCLK sync 
	radeon_pm_yclk_mclk_sync(rinfo);

       	/* M6, M7 and M9 so far ... */
	if (rinfo->is_mobility && rinfo->family <= CHIP_FAMILY_RV250) {
		radeon_pm_program_mode_reg(rinfo, 0x2000, 1);   
		radeon_pm_program_mode_reg(rinfo, 0x2001, 1);   
		radeon_pm_program_mode_reg(rinfo, 0x2002, 1);   
		radeon_pm_program_mode_reg(rinfo, 0x0132, 1);   
		radeon_pm_program_mode_reg(rinfo, 0x0032, 1); 
	}	

	OUTREG( MEM_SDRAM_MODE_REG,
		INREG( MEM_SDRAM_MODE_REG) |  MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); // Init Complete

	OUTREG( MEM_REFRESH_CNTL, 	memRefreshCntl);

	OUTREG( CRTC_GEN_CNTL, 		crtcGenCntl);
	OUTREG( CRTC2_GEN_CNTL, 	crtcGenCntl2);
	OUTREG( FP_GEN_CNTL, 		fp_gen_cntl);
	OUTREG( FP2_GEN_CNTL, 		fp2_gen_cntl);

	OUTREG( CRTC_MORE_CNTL, 	crtc_more_cntl);

	mdelay( 15);
}

// check whether VIP host is idle
// lock must be hold
static status_t Radeon_VIPIdle( 
	device_info *di )
{
	vuint8 *regs = di->regs;
	uint32 timeout;
	
	//Radeon_WaitForIdle( di, false, false );
	
	// if there is a stuck transaction, acknowledge that
	timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT );
	if( (timeout & RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_STAT) != 0 ) 
	{
		OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, 
			(timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_AK);
		return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
	}
	return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK;
}

static VOID i810_setscl(struct i2c_driver_t *st, UINT32 state)
{
	UCHAR *mmio = st->mmio_start_virtual;
	UINT32 val;

	OUTREG(mmio + st->ddc_base, (state ? SCL_VAL_OUT : 0) | 
		SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
	val = INREG(mmio + st->ddc_base);
}