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C++ CY_SET_REG32函数代码示例

原作者: [db:作者] 来自: [db:来源] 收藏 邀请

本文整理汇总了C++中CY_SET_REG32函数的典型用法代码示例。如果您正苦于以下问题：C++ CY_SET_REG32函数的具体用法？C++ CY_SET_REG32怎么用？C++ CY_SET_REG32使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。



在下文中一共展示了CY_SET_REG32函数的20个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。

示例1: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{
	/* Enable HALF_EN before trimming for the flash accelerator. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(24u);

	/* Disable HALF_EN since it is not required at this IMO frequency. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT12), 0x00000010u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00000000u);

	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000138u);

	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x0000FFFEu);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000005u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);
	while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);
}
开发者ID:andrey-mcs，项目名称:start-finish-system，代码行数:33，代码来源:cyfitter_cfg.c


示例2: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{
	/* Enable HALF_EN before trimming for the flash accelerator. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));

	/* Trim IMO BG based on desired frequency. */
	SetIMOBGTrims(48u);

	/* Going faster than 24MHz, so update trim value then adjust to new clock speed. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM45)));
	CyDelayUs(5u);
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (53u));

	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT02), 0x00000010u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT03), 0x00000010u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);

	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000000u);

}
开发者ID:e2forlife，项目名称:PSoC-W5100-Example1，代码行数:31，代码来源:cyfitter_cfg.c


示例3: SetIMOBGTrims

CY_CFG_SECTION
static void SetIMOBGTrims(uint8 imoFreq)
{
	CYPACKED typedef struct {
		uint8 freq;
		uint8 absolute;
		uint8 tmpco;
	} CYPACKED_ATTR imo_trim_entry_t;

	CYPACKED typedef struct {
		imo_trim_entry_t entries[4];
	} CYPACKED_ATTR imo_trim_table_t;

	static const imo_trim_table_t *imo_trim_table = (const imo_trim_table_t *)CYREG_SFLASH_IMO_MAXF0;
	static const uint32 IMO_TRIM_FREQ_TABLE_ENTRIES = sizeof(imo_trim_table->entries)/sizeof(imo_trim_table->entries[0]);

	int32 imoTrimIndex;
	uint8 setAbs;
	uint8 setTmpCo;

	/* Traverse the SFLASH IMO frequency-dependent bandgap trim table to
	 * locate the appropriate value to trim the IMO bandgap based on freq. */
	setAbs = CY_GET_REG8((const void *)CYREG_SFLASH_IMO_ABS4);
	setTmpCo = CY_GET_REG8((const void *)CYREG_SFLASH_IMO_TMPCO4);
	for (imoTrimIndex = ((int32)IMO_TRIM_FREQ_TABLE_ENTRIES)-1;
	     (imoTrimIndex >= 0) && (imoFreq <= imo_trim_table->entries[imoTrimIndex].freq);
	     imoTrimIndex--)
	{
		setAbs = imo_trim_table->entries[imoTrimIndex].absolute;
		setTmpCo = imo_trim_table->entries[imoTrimIndex].tmpco;
	}

	CY_SET_REG32((void *)CYREG_PWR_BG_TRIM4, setAbs);
	CY_SET_REG32((void *)CYREG_PWR_BG_TRIM5, setTmpCo);
}
开发者ID:gsgill112，项目名称:PSoC4_CY8CKIT-049_Tutorial，代码行数:35，代码来源:cyfitter_cfg.c


示例4: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{

	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(48u);
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* Setup phase aligned clocks */
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00002200u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00002200u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);

	/* CYDEV_PERI_PCLK_CTL5 Starting address: CYDEV_PERI_PCLK_CTL5 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL5), 0x00000040u);

	/* CYDEV_PERI_PCLK_CTL3 Starting address: CYDEV_PERI_PCLK_CTL3 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL3), 0x00000041u);

	(void)CyIntSetVector(7u, &CySysWdtIsr);
	CyIntEnable(7u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
开发者ID:Adrast，项目名称:16gr4404，代码行数:34，代码来源:cyfitter_cfg.c


示例5: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{
	/* Enable HALF_EN before trimming for the flash accelerator. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(24u);

	/* Disable HALF_EN since it is not required at this IMO frequency. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT03), 0x00000020u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT08), 0x00000010u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000001u);

	/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0x800000CFu);

	(void)CyIntSetVector(9u, &CySysWdtIsr);
	CyIntEnable(9u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
开发者ID:eshamidi，项目名称:PSoC2016，代码行数:32，代码来源:cyfitter_cfg.c


示例6: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{
	/* Enable HALF_EN before trimming for the flash accelerator. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));

	/* Trim IMO BG based on desired frequency. */
	SetIMOBGTrims(24u);

	/* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (25u));
	CyDelayCycles(5u);
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM21)));
	CyDelayUs(5u);

	/* Disable HALF_EN since it is not required at this IMO frequency. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT12), 0x00000010u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000033u);

}
开发者ID:Rensselaer-Motorsport，项目名称:Deprecated，代码行数:31，代码来源:cyfitter_cfg.c


示例7: WatchdogTimer_Unlock

/*****************************************************************************
* Function Name: WatchdogTimer_Unlock()
******************************************************************************
* Summary:
* Unlocks the watchdog timer to allow configuration changes.
*
* Parameters:
* None
*
* Return:
* None
*
* Theory:
* The CLK_SELECT register is written to, such that watchdog timer is now 
* unlocked. The watchdog timer registers can then be modified.
*
* Side Effects:
* None
*
* Note:
*
*****************************************************************************/
static void WatchdogTimer_Unlock(void)
{
    uint32 ClkSelectValue;

    ClkSelectValue = CY_GET_REG32(CYREG_CLK_SELECT) & ~CLK_SELECT_WDT_LOCK_SET01;
    CY_SET_REG32(CYREG_CLK_SELECT, ClkSelectValue | CLK_SELECT_WDT_LOCK_CLR0);
    CY_SET_REG32(CYREG_CLK_SELECT, ClkSelectValue | CLK_SELECT_WDT_LOCK_CLR1);
}
开发者ID:Ahamedjee，项目名称:PSoC-4-BLE，代码行数:30，代码来源:WatchdogTimer.c


示例8: BatteryLevel_Measure

/*****************************************************************************
* Function Name: BatteryLevel_Measure()
******************************************************************************
* Summary:
* Measures the current battery level.
*
* Parameters:
* None
*
* Return:
* None
*
* Theory:
* The function checks if the battery measurement enable flag is set in the 
* ADC ISR, and then measures the current battery level.
*
* Side Effects:
* None
*
* Note:
*
*****************************************************************************/
void BatteryLevel_Measure(void)
{
    uint16 adcCountsVref;
    static uint32 vddaVoltageMv;
    
    /* Disconnect the VREF pin from the chip and lose its existing voltage */
    CY_SET_REG32(CYREG_SAR_CTRL, CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x01 << 7));
    VrefInputPin_SetDriveMode(VrefInputPin_DM_STRONG);
    VrefInputPin_Write(0);
    CyDelayUs(10);
    
    /* Switch SAR reference to 1.024V to charge external cap */
    VrefInputPin_SetDriveMode(VrefInputPin_DM_ALG_HIZ);
    CY_SET_REG32(CYREG_SAR_CTRL, (CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x000000F0Lu)) | (0x00000040Lu) | (0x01Lu << 7));
    CyDelayUs(100);
    
    /* Switch the reference back to VDDA/2 for measuring the REF voltage */
    CY_SET_REG32(CYREG_SAR_CTRL, CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x01 << 7));
    CY_SET_REG32(CYREG_SAR_CTRL, (CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x00000070Lu)) | (0x00000060Lu));
    
    /* Enable channel 1 of the ADC, disable channel 0 */
    ADC_SetChanMask(0x02);
    
    /* Clear ADC interrupt triggered flag and start a new conversion */
    canMeasureBattery = false;
    ADC_StartConvert();
    while(true != canMeasureBattery);

    /* Since our ADC reference is VDDA/2, we get full scale (11-bit) at VDDA/2.
     * We can calculate VDDA by the formula:
     * VDDA = (VREF * (Full scale ADC out) * 2) / (ADC out for VREF)
     */
    adcCountsVref = ADC_GetResult16(1);
    if(adcCountsVref != 0)
    {
        vddaVoltageMv = ((uint32)VREF_VOLTAGE_MV * ADC_FULL_SCALE_OUT * 2) / (uint32)adcCountsVref;
    }
    
    /* Battery level is implemented as a linear plot from 2.0V to 3.0V 
     * Battery % level = (0.1 x VDDA in mV) - 200
     */
    batteryLevel = ((uint32)(vddaVoltageMv / 10)) - 200;
    if((batteryLevel > 100) && (batteryLevel < 230))
    {
        batteryLevel = 100;
    }
    else if(batteryLevel >= 230)
    {
        batteryLevel = 0;
    }
    
    
    /* Enable channel 0 again, disable channel 1 */
    ADC_SetChanMask(0x01);
    
    /* Enable bypass cap for the VDDA/2 reference */
    CY_SET_REG32(CYREG_SAR_CTRL, CY_GET_REG32(CYREG_SAR_CTRL) | (0x01 << 7));
}
开发者ID:Ahamedjee，项目名称:PSoC-4-BLE，代码行数:80，代码来源:BatteryLevel.c


示例9: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{

	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));

	/* Start the WCO */
	CySysClkWcoStart();
	(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM);    /* Switch to the low power mode */

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(24u);
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* Enable fast start mode for XO */
	CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
	/* Disable Crystal Stable Interrupt before enabling ECO */
	CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
	/* Start the ECO and do not check status since it is not needed for HFCLK */
	(void)CySysClkEcoStart(2000u);
	CyDelayUs(1500u); /* Wait to stabalize */

	/* Setup phase aligned clocks */
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL2, 0x0001DF00u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00000E00u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00001000u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u);

	/* CYDEV_PERI_PCLK_CTL8 Starting address: CYDEV_PERI_PCLK_CTL8 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL8), 0x00000042u);

	/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000042u);

	/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);

	/* CYDEV_PERI_PCLK_CTL1 Starting address: CYDEV_PERI_PCLK_CTL1 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL1), 0x00000041u);

	(void)CyIntSetVector(8u, &CySysWdtIsr);
	CyIntEnable(8u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
	/* Set Flash Cycles based on newly configured 24.00MHz HFCLK. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0011u));
}
开发者ID:mcisek，项目名称:balancing_robot，代码行数:58，代码来源:cyfitter_cfg.c


示例10: ILO_Calibration

/* 
**************************************************************
* This function returns the measured ILO frequency in kHz.
* NOTE: Disables Global Interrupts for an accurate measurement 
***************************************************************
*/
uint16 ILO_Calibration(void)
{
	uint16 WDTBegin, WDTEnd, WDTVal;
	uint32 SysTickBegin, SysTickEnd;
	
	/* Clear systick counter */
	CY_SET_REG32(CYREG_CM0_SYST_CVR, 0);
	
	/* Set systick reload to full 24-bit value */
	CY_SET_REG32(CYREG_CM0_SYST_RVR, 0x0FFFFFF);

	/* Enable systick counter */
	CY_SET_REG32(CYREG_CM0_SYST_CSR,(uint32)5u);
	
	CyGlobalIntDisable;
	WDTBegin = CySysWdtReadCount();
	
	/* Wait for WDT transition to make sure we start on an edge */
	do
	{
		WDTVal = CySysWdtReadCount();
	}
	while(WDTVal  == WDTBegin);
	
	/* Read initial Systick value */
	SysTickBegin = CY_GET_REG32(CYREG_CM0_SYST_CVR); 
	
	/* This is the count at the edge we waited for */
	WDTBegin = WDTVal;
	
	/* Set up our end as ILO_MEAS_CYCLES more ILO cycles */
	WDTEnd = WDTVal + ILO_MEAS_CYCLES;
	
	/* Waitt here for our WDT end count to be reached */
	while (CySysWdtReadCount() != WDTEnd);
	
	/* Read ending Systick value */
	SysTickEnd = CY_GET_REG32(CYREG_CM0_SYST_CVR); 
	
	CyGlobalIntEnable;
	
	/* Check for overflow */
	//regData = CM0->SYST_CSR; ///Countflag
   ///if ( regData & BIT16 ) return DEFAULT_ILO; /// COUNTFLAG is set   
   /// Check that the SYST_CSR COUNTFLAG has not been set. If set it means there is overflow    
   /// If overflow return 32KHz
	
	/* SysTick is a down counter, so SysTickBegin - SysTickEnd is the number of SYSCLK
	*	cycles in ILO_MEAS_CYCLES rising edges of ILO clock. This outputs the ILO freq 
	*	in kHz
	*/
	return (uint16)((CYDEV_BCLK__SYSCLK__KHZ*ILO_MEAS_CYCLES)/(SysTickBegin - SysTickEnd));
	
	
	
	}
开发者ID:kyoung2112，项目名称:psoc40xx-calibrated-ILO-sleep，代码行数:62，代码来源:ilomeasurement.c


示例11: AMux_1_Unset

/*******************************************************************************
* Function Name: AMux_1_Unset
********************************************************************************
* Summary:
*  This function is used to clear a particular channel from being active on the
*  AMux.
*
* Parameters:  
*   channel - The mux channel input to mark inactive
*
* Return:
*   void
*
*******************************************************************************/
void AMux_1_Unset(uint8 channel)
{
	switch (channel) {
		case 0u:
			CY_SET_REG32((void CYXDATA *)CYREG_HSIOM_PORT_SEL3, (CY_GET_REG32((void CYXDATA *)CYREG_HSIOM_PORT_SEL3) & 0xfff9ffffu));
			break;
		case 1u:
			CY_SET_REG32((void CYXDATA *)CYREG_HSIOM_PORT_SEL0, (CY_GET_REG32((void CYXDATA *)CYREG_HSIOM_PORT_SEL0) & 0xffff9fffu));
			break;
		default:
			break;
	}
}
开发者ID:CoroBot，项目名称:Spark_Firmware，代码行数:27，代码来源:cyfitter_cfg.c


示例12: PrISM_PulseIndicator_Init

/*******************************************************************************
* Function Name: PrISM_PulseIndicator_Init
********************************************************************************
*
* Summary:
*  Initialize component's parameters to the parameters set by user in the 
*  customizer of the component placed onto schematic. Usually called in 
*  PrISM_PulseIndicator_Start().
*
* Parameters:  
*  None.
*
* Return: 
*  None.
*
*******************************************************************************/
void PrISM_PulseIndicator_Init(void) 
{
    uint8 enableInterrupts;
    
    /* Writes Seed value, polynom value and density provided by customizer */
    PrISM_PulseIndicator_WriteSeed(PrISM_PulseIndicator_SEED);
    PrISM_PulseIndicator_WritePolynomial(PrISM_PulseIndicator_POLYNOM);
    PrISM_PulseIndicator_WritePulse0(PrISM_PulseIndicator_DENSITY0);
    PrISM_PulseIndicator_WritePulse1(PrISM_PulseIndicator_DENSITY1);
    
    enableInterrupts = CyEnterCriticalSection();
    /* Set FIFO0_CLR bit to use FIFO0 as a simple one-byte buffer*/
    #if (PrISM_PulseIndicator_RESOLUTION <= 8u)      /* 8bit - PrISM */
        PrISM_PulseIndicator_AUX_CONTROL_REG |= PrISM_PulseIndicator_FIFO0_CLR;
    #elif (PrISM_PulseIndicator_RESOLUTION <= 16u)   /* 16bit - PrISM */
        CY_SET_REG16(PrISM_PulseIndicator_AUX_CONTROL_PTR, CY_GET_REG16(PrISM_PulseIndicator_AUX_CONTROL_PTR) | 
                                        PrISM_PulseIndicator_FIFO0_CLR | PrISM_PulseIndicator_FIFO0_CLR << 8u);
    #elif (PrISM_PulseIndicator_RESOLUTION <= 24u)   /* 24bit - PrISM */
        CY_SET_REG24(PrISM_PulseIndicator_AUX_CONTROL_PTR, CY_GET_REG24(PrISM_PulseIndicator_AUX_CONTROL_PTR) |
                                        PrISM_PulseIndicator_FIFO0_CLR | PrISM_PulseIndicator_FIFO0_CLR << 8u );
        CY_SET_REG24(PrISM_PulseIndicator_AUX_CONTROL2_PTR, CY_GET_REG24(PrISM_PulseIndicator_AUX_CONTROL2_PTR) | 
                                        PrISM_PulseIndicator_FIFO0_CLR );
    #else                                 /* 32bit - PrISM */
        CY_SET_REG32(PrISM_PulseIndicator_AUX_CONTROL_PTR, CY_GET_REG32(PrISM_PulseIndicator_AUX_CONTROL_PTR) |
                                        PrISM_PulseIndicator_FIFO0_CLR | PrISM_PulseIndicator_FIFO0_CLR << 8u );
        CY_SET_REG32(PrISM_PulseIndicator_AUX_CONTROL2_PTR, CY_GET_REG32(PrISM_PulseIndicator_AUX_CONTROL2_PTR) |
                                        PrISM_PulseIndicator_FIFO0_CLR | PrISM_PulseIndicator_FIFO0_CLR << 8u );
    #endif                                /* End PrISM_PulseIndicator_RESOLUTION */
    CyExitCriticalSection(enableInterrupts);
    
    #if(!PrISM_PulseIndicator_PULSE_TYPE_HARDCODED)
        /* Writes density type provided by customizer */
        if(PrISM_PulseIndicator_GREATERTHAN_OR_EQUAL == 0 )
        {
            PrISM_PulseIndicator_CONTROL_REG |= PrISM_PulseIndicator_CTRL_COMPARE_TYPE0_GREATER_THAN_OR_EQUAL;
        }
        else
        {
            PrISM_PulseIndicator_CONTROL_REG &= ~PrISM_PulseIndicator_CTRL_COMPARE_TYPE0_GREATER_THAN_OR_EQUAL;
        }
    
        if(PrISM_PulseIndicator_GREATERTHAN_OR_EQUAL == 0)
        {
            PrISM_PulseIndicator_CONTROL_REG |= PrISM_PulseIndicator_CTRL_COMPARE_TYPE1_GREATER_THAN_OR_EQUAL;
        }
        else
        {
            PrISM_PulseIndicator_CONTROL_REG &= ~PrISM_PulseIndicator_CTRL_COMPARE_TYPE1_GREATER_THAN_OR_EQUAL;
        }
    #endif /* End PrISM_PulseIndicator_PULSE_TYPE_HARDCODED */
}
开发者ID:marcelocoelho，项目名称:Pulse-Firmware，代码行数:67，代码来源:PrISM_PulseIndicator.c


示例13: AMux_Unset

/*******************************************************************************
* Function Name: AMux_Unset
********************************************************************************
* Summary:
*  This function is used to clear a particular channel from being active on the
*  AMux.
*
* Parameters:  
*   channel - The mux channel input to mark inactive
*
* Return:
*   void
*
*******************************************************************************/
void AMux_Unset(uint8 channel)
{
	switch (channel) {
		case 0u:
			CY_SET_REG32((void CYXDATA *)CYREG_SAR_MUX_SWITCH_CLEAR0, (0x80u));
			break;
		case 1u:
			CY_SET_REG32((void CYXDATA *)CYREG_HSIOM_PORT_SEL0, (CY_GET_REG32((void CYXDATA *)CYREG_HSIOM_PORT_SEL0) & 0xfffffff8u));
			CY_SET_REG32((void CYXDATA *)CYREG_SAR_MUX_SWITCH_CLEAR0, (0x80000u));
			break;
		default:
			break;
	}
}
开发者ID:remixvit，项目名称:ExpoController，代码行数:28，代码来源:cyfitter_cfg.c


示例14: PrISM_PulseIndicator_2_RestoreConfig

/*******************************************************************************
* Function Name: PrISM_PulseIndicator_2_RestoreConfig
********************************************************************************
*
* Summary:
*  Restores the current user configuration.
*
* Parameters:  
*  None.
*
* Return: 
*  None.
*
* Global Variables:
*  PrISM_PulseIndicator_2_backup - used when non-retention registers are restored.
*
*******************************************************************************/
void PrISM_PulseIndicator_2_RestoreConfig(void) 
{
    #if (CY_UDB_V0)
    
        uint8 enableInterrupts;
        
        #if(!PrISM_PulseIndicator_2_PULSE_TYPE_HARDCODED)
            PrISM_PulseIndicator_2_CONTROL_REG = PrISM_PulseIndicator_2_backup.cr;
        #endif /* End PrISM_PulseIndicator_2_PULSE_TYPE_HARDCODED */

        CY_SET_REG8(PrISM_PulseIndicator_2_SEED_COPY_PTR, PrISM_PulseIndicator_2_backup.seed_copy);
        CY_SET_REG8(PrISM_PulseIndicator_2_SEED_PTR, PrISM_PulseIndicator_2_backup.seed);
        PrISM_PulseIndicator_2_WritePolynomial(PrISM_PulseIndicator_2_backup.polynom);
        PrISM_PulseIndicator_2_WritePulse0(PrISM_PulseIndicator_2_backup.density0);
        PrISM_PulseIndicator_2_WritePulse1(PrISM_PulseIndicator_2_backup.density1);
        
        enableInterrupts = CyEnterCriticalSection();
        /* Set FIFO0_CLR bit to use FIFO0 as a simple one-byte buffer*/
        #if (PrISM_PulseIndicator_2_RESOLUTION <= 8u)      /* 8bit - PrISM */
            PrISM_PulseIndicator_2_AUX_CONTROL_REG |= PrISM_PulseIndicator_2_FIFO0_CLR;
        #elif (PrISM_PulseIndicator_2_RESOLUTION <= 16u)   /* 16bit - PrISM */
            CY_SET_REG16(PrISM_PulseIndicator_2_AUX_CONTROL_PTR, CY_GET_REG16(PrISM_PulseIndicator_2_AUX_CONTROL_PTR) | 
                                            PrISM_PulseIndicator_2_FIFO0_CLR | PrISM_PulseIndicator_2_FIFO0_CLR << 8u);
        #elif (PrISM_PulseIndicator_2_RESOLUTION <= 24)   /* 24bit - PrISM */
            CY_SET_REG24(PrISM_PulseIndicator_2_AUX_CONTROL_PTR, CY_GET_REG24(PrISM_PulseIndicator_2_AUX_CONTROL_PTR) |
                                            PrISM_PulseIndicator_2_FIFO0_CLR | PrISM_PulseIndicator_2_FIFO0_CLR << 8u );
            CY_SET_REG24(PrISM_PulseIndicator_2_AUX_CONTROL2_PTR, CY_GET_REG24(PrISM_PulseIndicator_2_AUX_CONTROL2_PTR) | 
                                            PrISM_PulseIndicator_2_FIFO0_CLR );
        #else                                 /* 32bit - PrISM */
            CY_SET_REG32(PrISM_PulseIndicator_2_AUX_CONTROL_PTR, CY_GET_REG32(PrISM_PulseIndicator_2_AUX_CONTROL_PTR) |
                                            PrISM_PulseIndicator_2_FIFO0_CLR | PrISM_PulseIndicator_2_FIFO0_CLR << 8u );
            CY_SET_REG32(PrISM_PulseIndicator_2_AUX_CONTROL2_PTR, CY_GET_REG32(PrISM_PulseIndicator_2_AUX_CONTROL2_PTR) |
                                            PrISM_PulseIndicator_2_FIFO0_CLR | PrISM_PulseIndicator_2_FIFO0_CLR << 8u );
        #endif                                /* End PrISM_PulseIndicator_2_RESOLUTION */
        CyExitCriticalSection(enableInterrupts);
   
    #else   /* CY_UDB_V1 */

        #if(!PrISM_PulseIndicator_2_PULSE_TYPE_HARDCODED)
            PrISM_PulseIndicator_2_CONTROL_REG = PrISM_PulseIndicator_2_backup.cr;
        #endif /* End PrISM_PulseIndicator_2_PULSE_TYPE_HARDCODED */

        CY_SET_REG8(PrISM_PulseIndicator_2_SEED_COPY_PTR, PrISM_PulseIndicator_2_backup.seed_copy);
        CY_SET_REG8(PrISM_PulseIndicator_2_SEED_PTR, PrISM_PulseIndicator_2_backup.seed);
        PrISM_PulseIndicator_2_WritePolynomial(PrISM_PulseIndicator_2_backup.polynom);
    
    #endif  /* End CY_UDB_V0 */
}
开发者ID:marcelocoelho，项目名称:Pulse-Firmware，代码行数:65，代码来源:PrISM_PulseIndicator_2_PM.c


示例15: WatchdogTimer_Lock

/*****************************************************************************
* Function Name: WatchdogTimer_Lock()
******************************************************************************
* Summary:
* Locks the watchdog timer to prevent configuration changes.
*
* Parameters:
* None
*
* Return:
* None
*
* Theory:
* The CLK_SELECT register is written to, such that watchdog timer is now 
* locked. Any further changes to watchdog timer registers are then ignored.
*
* Side Effects:
* None
*
* Note:
*
*****************************************************************************/
static void WatchdogTimer_Lock(void)
{
    uint32 ClkSelectValue;

    ClkSelectValue = CY_GET_REG32(CYREG_CLK_SELECT) | CLK_SELECT_WDT_LOCK_SET01;
    CY_SET_REG32(CYREG_CLK_SELECT, ClkSelectValue);
}
开发者ID:Ahamedjee，项目名称:PSoC-4-BLE，代码行数:29，代码来源:WatchdogTimer.c


示例16: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{
	/* Enable HALF_EN before trimming for the flash accelerator. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(48u);
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT07), 0x00000010u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT08), 0x00000020u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x82000000u);

	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00080000u);

	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x8000001Du);

	/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0x8000002Fu);

	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
开发者ID:elishatam，项目名称:PSOC4Pioneer，代码行数:30，代码来源:cyfitter_cfg.c


示例17: calibrate_opamp_offset_trim

void calibrate_opamp_offset_trim(settings_t *newsettings, int microamps, progress_callback_t progress_callback) {
    state.calibrating = 1;
	int high_value = microamps / DEFAULT_DAC_HIGH_GAIN;
	int low_value = 100000 / DEFAULT_DAC_HIGH_GAIN; // Approx 100mA
    int high_current, low_current;
    IDAC_Low_SetValue(0);

	// Find the best setting for the opamp trim
    int min_offset = INT_MIN;
    int min_offset_idx = 0;
    
	for(int i = 0; i < MAX_OA_OFFSET_STEPS; i++) {
        progress_callback(i+1,MAX_OA_OFFSET_STEPS);
		CY_SET_REG32(Opamp_cy_psoc4_abuf__OA_OFFSET_TRIM, i);
		
        IDAC_High_SetValue(high_value);
        vTaskDelay(configTICK_RATE_HZ);
        high_current = get_raw_current_usage() - newsettings->calibration_settings.adc_current_offset;

        IDAC_High_SetValue(low_value);
        vTaskDelay(configTICK_RATE_HZ);
        low_current = get_raw_current_usage() - newsettings->calibration_settings.adc_current_offset;

        int offset = (high_value * low_current - low_value * high_current) / (high_value - low_value);
		if(offset <= 0 && offset > min_offset) {
            min_offset = offset;
            min_offset_idx = i;
		}
	}
    set_opamp_offset_trim(newsettings, min_offset_idx);

	set_current(0);
    state.calibrating = 0;
}
开发者ID:ACORELL，项目名称:reload-pro，代码行数:34，代码来源:calibrate.c


示例18: Phase_Counter_WritePeriod

/*******************************************************************************
* Function Name: Phase_Counter_WritePeriod
********************************************************************************
* Summary:
* Changes the period of the counter.  The new period 
* will be loaded the next time terminal count is detected.
*
* Parameters:  
*  period: (uint32) A value of 0 will result in
*         the counter remaining at zero.  
*
* Return: 
*  void
*
*******************************************************************************/
void Phase_Counter_WritePeriod(uint32 period) 
{
    #if(Phase_Counter_UsingFixedFunction)
        CY_SET_REG16(Phase_Counter_PERIOD_LSB_PTR,(uint16)period);
    #else
        CY_SET_REG32(Phase_Counter_PERIOD_LSB_PTR, period);
    #endif /* (Phase_Counter_UsingFixedFunction) */
}
开发者ID:tslator，项目名称:DualBoard-043，代码行数:23，代码来源:Phase_Counter.c


示例19: HeartbeatCounter_WritePeriod

/*******************************************************************************
* Function Name: HeartbeatCounter_WritePeriod
********************************************************************************
* Summary:
* Changes the period of the counter.  The new period 
* will be loaded the next time terminal count is detected.
*
* Parameters:  
*  period: (uint32) A value of 0 will result in
*         the counter remaining at zero.  
*
* Return: 
*  void
*
*******************************************************************************/
void HeartbeatCounter_WritePeriod(uint32 period) 
{
    #if(HeartbeatCounter_UsingFixedFunction)
        CY_SET_REG16(HeartbeatCounter_PERIOD_LSB_PTR,(uint16)period);
    #else
        CY_SET_REG32(HeartbeatCounter_PERIOD_LSB_PTR, period);
    #endif /* (HeartbeatCounter_UsingFixedFunction) */
}
开发者ID:ponioj，项目名称:embedded，代码行数:23，代码来源:HeartbeatCounter.c


示例20: ClockSetup

CY_CFG_SECTION
static void ClockSetup(void)
{

	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));

	/* Start the WCO */
	CySysClkWcoStart();
	CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
	(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM);    /* Switch to the low power mode */

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(48u);
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);

	/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);


	/* Enable fast start mode for XO */
	CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
	/* Disable Crystal Stable Interrupt before enabling ECO */
	CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
	/* Start the ECO and do not check status since it is not needed for HFCLK */
	(void)CySysClkEcoStart(2000u);
	CyDelayUs(1500u); /* Wait to stabalize */

	/* Setup phase aligned clocks */
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00001900u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);

	/* CYDEV_PERI_PCLK_CTL1 Starting address: CYDEV_PERI_PCLK_CTL1 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL1), 0x00000040u);

	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
}
开发者ID:Adrast，项目名称:16gr4404，代码行数:45，代码来源:cyfitter_cfg.c



注：本文中的CY_SET_REG32函数示例整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。

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