/**
*
* Interrupt control: Set reduced interrupt configuration.
*
* @param    vector - interrupt number [0..94].
* @param    level  - priority is the new priority for the IRQ source. 0x00 is highest, 0xFF lowest.
*
* @return   none
*
*****************************************************************************/
void hal_interrupt_set_level(int vector, int level)
{
    cyg_uint32 dwRegValue;
    
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
    CYG_ASSERT(level >= 0 && level <= 7, "Invalid level");

    //
    // Determine the register to write to using the vector.
    //
    HAL_READ_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + 
            XSCUGIC_PRIORITY_OFFSET_CALC(vector), dwRegValue);

    //
    // Shift and Mask the correct bits for the priority and trigger in the
    // register
    //
    dwRegValue &= ~(XSCUGIC_PRIORITY_MASK << (( vector % 4) * 8));
    dwRegValue |= level << (( vector % 4) * 8);

    //
    // Write the value back to the register.
    //
    HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + XSCUGIC_PRIORITY_OFFSET_CALC(vector),
                dwRegValue);
}

void
fatfs_node_cache_flush(fatfs_disk_t *disk)
{
    fatfs_node_t *node, *next_node;

    node = node_list_get_head(&disk->live_nlist);

    while (NULL != node)
    {
        next_node = node_list_get_next(node);
        node_list_remove(&disk->live_nlist, node);
        if (!node_hash_remove(&disk->node_hash, node))
            CYG_ASSERT(false, "Node not in hash");
        node_pool_free(disk, node);
        node = next_node;
    }

    node = node_list_get_head(&disk->dead_nlist);

    while (NULL != node)
    {
        next_node = node_list_get_next(node);
        node_list_remove(&disk->dead_nlist, node);
        if (!node_hash_remove(&disk->node_hash, node))
            CYG_ASSERT(false, "Node not in hash");
        node_pool_free(disk, node);
        node = next_node;
    }

    SANITY_CHECK();
}

static void
node_hash_check(fatfs_hash_table_t *tbl)
{
    int i, n;

    n = 0;
    for (i = 0; i < tbl->size; i++)
    {
        fatfs_node_t *lnode, *pnode;

        pnode = NULL;
        lnode = tbl->nodes[i];

        while (lnode != NULL)
        {
            if (pnode != NULL)
            {
                int c = strcasecmp(pnode->dentry.filename, lnode->dentry.filename);
                CYG_ASSERT(c <= 0, "hash table not sorted");
                CYG_ASSERT(pnode->dentry.parent_cluster != lnode->dentry.parent_cluster ||
                           0 != c, "duplicated node in hash table");
            }
            n++;
            pnode = lnode;
            lnode = lnode->hash_next;
        }
    }
    CYG_ASSERTC(tbl->n == n);
}

void hal_interrupt_set_level(int vector, int level)
{
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
    CYG_ASSERT(level >= 0 && level <= 7, "Invalid level");

}

void 
hal_interrupt_configure(int vector, int level, int up)
{
    cyg_uint32 pvr;

    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
    if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
        // Can't do much with non-external interrupts
        return;
    }
//    diag_printf("%s(%d, %d, %d)\n", __FUNCTION__, vector, level, up);
    HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
    pvr &= _CSB281_EPIC_PVR_M;  // Preserve mask
    pvr |= vector;
    if (level) {
        pvr |= _CSB281_EPIC_PVR_S;
    } else {
        pvr &= ~_CSB281_EPIC_PVR_S;
    }
    if (up) {
        pvr |= _CSB281_EPIC_PVR_P;
    } else {
        pvr &= ~_CSB281_EPIC_PVR_P;
    }
    HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
}

void hal_diag_write_char(char c)
{
    static int  diag_index = 0;
    static unsigned char diag_buffer[128];

    CYG_ASSERT(diag_index < 128, "Diagnostic buffer overflow");
    
    diag_buffer[diag_index++] = (unsigned char) c;
    if (('\n' == c) || (128 == diag_index)) {
        if ((-1 != auxiliary_console_id) && synth_auxiliary_running) {
            synth_auxiliary_xchgmsg(auxiliary_console_id, 0, 0, 0, diag_buffer, diag_index, (int *) 0, (unsigned char*) 0, (int *)0, 0);
            diag_index = 0;
        } else {
            int     written;
            unsigned char* next    = diag_buffer;

            while (diag_index > 0) {
                written = cyg_hal_sys_write(1, next, diag_index);
                if (written > 0) {
                    diag_index -= written;
                    next       += written;
                } else if ((-CYG_HAL_SYS_EINTR != written) && (-CYG_HAL_SYS_EAGAIN != written)) {
                    CYG_FAIL("Unexpected error writing to stdout.");
                    diag_index = 0;
                    break;
                }
            }
            CYG_ASSERT(0 == diag_index, "All data should have been written out");
            diag_index = 0;
            cyg_hal_sys_fdatasync(1);
        }
    }
}

static void
node_hash_not_found_check(fatfs_disk_t *disk,
                          const char   *name,
                          unsigned int  namelen,
                          unsigned int  parent_cluster)
{
    fatfs_node_t* node;

    node = node_list_get_head(&disk->live_nlist);
    while (NULL != node)
    {
        if (node->dentry.parent_cluster == parent_cluster          &&
                namelen == strlen(node->dentry.filename)               &&
                0 == strncasecmp(name, node->dentry.filename, namelen))
            CYG_ASSERT(false, "node not found in hash, "
                       "but exists in live list");
        node = node_list_get_next(node);
    }

    node = node_list_get_head(&disk->dead_nlist);
    while (NULL != node)
    {
        if (node->dentry.parent_cluster == parent_cluster          &&
                namelen == strlen(node->dentry.filename)               &&
                0 == strncasecmp(name, node->dentry.filename, namelen))
            CYG_ASSERT(false, "node not found in hash, "
                       "but exists in dead list");
        node = node_list_get_next(node);
    }
}

reconos_slot_t *find_free_slot(rthread_attr_t *t) {
    uint8 possible_slots[NUM_OSIFS];
    reconos_bitstream_t *possible_bitstreams[NUM_OSIFS];
    uint8 num_possible_slots = 0;
    int i, j;

    CYG_ASSERT( t->flags & RTHREAD_ATTR_IS_DYNAMIC, "trying to reconfigure a static thread" );
    CYG_ASSERT( t->circuit->num_bitstreams > 0, "no bitstreams available for thread" );

    for (i = 0; i < NUM_OSIFS; i++) {
        for (j = 0; j < t->circuit->num_bitstreams; j++) {
            if (t->circuit->bitstreams[j]->slot_num == i) {
                possible_slots[num_possible_slots] = i;
                possible_bitstreams[num_possible_slots++] = 
                    t->circuit->bitstreams[j];
            }
        }
    }

    for (i = 0; i < num_possible_slots; i++) {
        // either free or not-executing slots are okay
        j = possible_slots[i];
        if (reconos_slots[j].state == FREE ) {
//            || reconos_slots[j].state == READY) {
           return &reconos_slots[j];
        }
    }
    return NULL;
}

static rcv_req_reply_t
serial_data_rcv_req(serial_channel *chan, int avail, 
                    int* space_avail, unsigned char** space)
{
    cbuf_t *cbuf = &chan->in_cbuf;
    int gap;

#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_SOFTWARE
    // When there is software flow-control, force the serial device
    // driver to use the single-char xmt/rcv functions, since these
    // have to make policy decision based on the data. Rcv function
    // may also have to transmit data to throttle the xmitter.
    if (chan->config.flags & (CYGNUM_SERIAL_FLOW_XONXOFF_TX|CYGNUM_SERIAL_FLOW_XONXOFF_RX))
        return CYG_RCV_DISABLED;
#endif

    CYG_ASSERT(false == cbuf->block_mode_xfer_running,
               "Attempting new block transfer while another is running");
    // Check for space
    gap = cbuf->nb;
    if (gap == cbuf->len)
        return CYG_RCV_FULL;

#ifdef CYGDBG_USE_ASSERTS
    cbuf->block_mode_xfer_running = true;
#endif

    if (0 == gap) {
        // Buffer is empty. Reset put/get indexes to get max transfer in
        // one chunk.
        cbuf->get = 0;
        cbuf->put = 0;
        gap = cbuf->len;
    } else {
        // Free space (G = get, P = put, x = data, . = empty)
        //  positive: xxxxP.....Gxxx
        //  negative: ..GxxxxxP.....        [offer last chunk only]

        // First try for a gap between put and get locations
       
       	gap = cbuf->get - cbuf->put;
       
        if (gap < 0) {
            // If failed, the gap is between put and the end of buffer
            gap = cbuf->len - cbuf->put;
        }
    }

    if (avail < gap) gap = avail;   // bound by what's available from hw
    
    *space_avail = gap;
    *space = &cbuf->data[cbuf->put];

    CYG_ASSERT((gap+cbuf->nb) <= cbuf->len, "Buffer will overflow");
    CYG_ASSERT(cbuf->put < cbuf->len, "Invalid put ptr");
    CYG_ASSERT(cbuf->get < cbuf->len, "Invalid get ptr");

    return CYG_RCV_OK;
}

externC void cyg_drv_interrupt_attach( cyg_handle_t interrupt )
{
    cyg_interrupt *intr = (cyg_interrupt *)interrupt;
    
    CYG_REPORT_FUNCTION();

    CYG_ASSERT( intr->vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
    CYG_ASSERT( intr->vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");

    HAL_INTERRUPT_SET_LEVEL( intr->vector, intr->priority );
    
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN

    CYG_ASSERT( intr->next == NULL , "cyg_interrupt already on a list");

    {
        cyg_uint32 index;

        HAL_TRANSLATE_VECTOR( intr->vector, index );

        if( chain_list[index] == NULL ) 
        {
            // First Interrupt on this chain, just assign it and
            // register the chain_isr with the HAL.
        
            chain_list[index] = intr;

            HAL_INTERRUPT_ATTACH( intr->vector, chain_isr, 
                                  &chain_list[index], NULL );
        } 
        else
        {
            // There are already interrupts chained, add this one into
            // the chain in priority order.
        
            cyg_interrupt **p = &chain_list[index];

            while( *p != NULL )
            {
                cyg_interrupt *n = *p;
                
                if( n->priority < intr->priority ) break;
            
                p = &n->next;
            }
            intr->next = *p;
            *p = intr;
        }
    }
    
#else
    
    HAL_INTERRUPT_ATTACH( intr->vector, intr->isr, intr->data, intr );

#endif    
    
    CYG_REPORT_RETURN();    
}

static void cyg_httpd_init(cyg_addrword_t arg)
{
    int i;
    int err = 0;

    /* Delay for a configurable length of time to give the application
     * a chance to get going, or even complete, without interference
     * from the HTTPD.
     */
    if( CYGNUM_HTTPD_SERVER_DELAY > 0 )
    {
        cyg_thread_delay( CYGNUM_HTTPD_SERVER_DELAY );
    }
    
    server_address.sin_family = AF_INET;
    server_address.sin_len = sizeof(server_address);
    server_address.sin_addr.s_addr = INADDR_ANY;
    server_address.sin_port = htons(CYGNUM_HTTPD_SERVER_PORT);

    /* Get the network going. This is benign if the application has
     * already done this.
     */
    init_all_network_interfaces();

    /* Create and bind the server socket.
     */
    server_socket = socket( AF_INET, SOCK_STREAM, IPPROTO_TCP );
    CYG_ASSERT( server_socket > 0, "Socket create failed");

    err = bind( server_socket, (struct sockaddr *)&server_address,
                sizeof(server_address) );
    CYG_ASSERT( err == 0, "bind() returned error");

    err = listen( server_socket, SOMAXCONN );
    CYG_ASSERT( err == 0, "listen() returned error" );

    /* If we are configured to have more than one server thread,
     * create them now.
     */
    for( i = 1; i < CYGNUM_HTTPD_THREAD_COUNT; i++ )
    {
        cyg_thread_create( CYGNUM_HTTPD_THREAD_PRIORITY,
                           cyg_httpd_server,
                           0,
                           "HTTPD",
                           &httpd_stacks[i][0],
                           sizeof(httpd_stacks[i]),
                           &httpd_thread[i],
                           &httpd_thread_object[i]
            );
    
        cyg_thread_resume( httpd_thread[i] );
    }

    /* Now go be a server ourself.
     */
    cyg_httpd_server(arg);
}

void hal_interrupt_set_level(int vector, int level)
{
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
    CYG_ASSERT(level >=0 level <= 15, "Invalid level");

    HAL_WRITE_UINT8(MAC7100_INTC_ICR(MAC7100_INTC_BASE,vector),
                    MAC7100_INTC_INT_LEVEL(level));
}

externC void cyg_drv_interrupt_acknowledge( cyg_vector_t vector )
{
//    CYG_REPORT_FUNCTION();

    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");    
    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");

    HAL_INTERRUPT_ACKNOWLEDGE( vector );

//    CYG_REPORT_RETURN();    
}

void
hal_interrupt_set_level(int vector, int level)
{
    CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");    
    CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)                         
                && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); 
                                                                         
    cyg_hal_ILVL_table[vector] = level;

    hal_interrupt_update_level(vector);
}

externC void cyg_drv_interrupt_level( cyg_vector_t vector, cyg_priority_t level )
{
    CYG_REPORT_FUNCTION();
    CYG_REPORT_FUNCARG2("vector = %d, level = %d", vector, level);

    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");    
    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");

    HAL_INTERRUPT_SET_LEVEL( vector, level );

    CYG_REPORT_RETURN();
}

externC void cyg_drv_interrupt_unmask_intunsafe( cyg_vector_t vector )
{
    CYG_REPORT_FUNCTION();
    CYG_REPORT_FUNCARG1("vector=%d", vector);

    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");    
    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
    
    HAL_INTERRUPT_UNMASK( vector );

    CYG_REPORT_RETURN();
}

// ------------------------------------------------------------------------
// HANDLER THREAD ENTRY ROUTINE
// This waits on the DSR to tell it to run:
static void
alarm_thread(cyg_addrword_t param)
{
    // This is from the logical ethernet dev; it calls those delivery
    // functions who need attention.
    extern void eth_drv_run_deliveries( void );

    // This is from the logical ethernet dev; it tickles somehow
    // all ethernet devices in case one is wedged.
    extern void eth_drv_tickle_devices( void );

    while ( 1 ) {
        int spl;
        int x;
#ifdef CYGPKG_NET_FAST_THREAD_TICKLE_DEVS
        cyg_tick_count_t later = cyg_current_time();
        later += CYGNUM_NET_FAST_THREAD_TICKLE_DEVS_DELAY;
        x = cyg_flag_timed_wait(
            &alarm_flag,
            -1,
            CYG_FLAG_WAITMODE_OR | CYG_FLAG_WAITMODE_CLR,
            later );
#else
        x = cyg_flag_wait(
            &alarm_flag,
            -1,
            CYG_FLAG_WAITMODE_OR | CYG_FLAG_WAITMODE_CLR );

        CYG_ASSERT( 3 & x, "Lost my bits" );
#endif // CYGPKG_NET_FAST_THREAD_TICKLE_DEVS
        CYG_ASSERT( !((~3) & x), "Extra bits" );

        spl = cyg_splinternal();

        CYG_ASSERT( 0 == spl, "spl nonzero" );

        if ( 2 & x )
            eth_drv_run_deliveries();
#ifdef CYGPKG_NET_FAST_THREAD_TICKLE_DEVS
        // This is in the else clause for "do we deliver" because the
        // network stack might have continuous timing events anyway - so
        // the timeout would not occur, x would be 1 every time.
        else // Tickle the devices...
            eth_drv_tickle_devices();
#endif // CYGPKG_NET_FAST_THREAD_TICKLE_DEVS

        if ( 1 & x )
            do_timeout();

        cyg_splx(spl);
    }
}

static int dspi_set_config(cyg_spi_device* device, cyg_uint32 key,
                           const void* buf, cyg_uint32* len)
{
    cyg_spi_freescale_dspi_device_t* dspi_device =
          (cyg_spi_freescale_dspi_device_t*) device;
    cyg_spi_freescale_dspi_bus_t* dspi_bus =
          (cyg_spi_freescale_dspi_bus_t*) device->spi_bus;

    cyg_uint32 regval;
    ctar_br_t brs;

    switch (key) {
    case CYG_IO_SET_CONFIG_SPI_CLOCKRATE :
        // Sanity check
        if (NULL == len) {
            CYG_ASSERT (false, "Freescale DSPI:"
                      " Null pointer as len argument for dspi_set_config().");
            return -1;
        } else if (sizeof(cyg_uint32) != *len) {
            CYG_ASSERT (false, "Freescale DSPI:"
                        " Invalid length with dspi_set_config().");
            return -1;
        } else if (NULL == buf) {
            CYG_ASSERT (false, "Freescale DSPI:"
                        " Null pointer as buf argument for dspi_set_config().");
            return -1;
        } else {
            // Get divider bits
            if (!dspi_ctar_brbf(&dspi_device->clocking, &brs,
                                   ctar_br, ctar_pbr, (cyg_uint32 *)buf, dspi_bus->clock_freq))
            {
                // Update the cache of the configuration register settings.
                regval = dspi_device->clocking.dspi_ctar;
                regval &= ~(FREESCALE_DSPI_CTAR_BR_M |
                            FREESCALE_DSPI_CTAR_PBR_M);
                regval |= FREESCALE_DSPI_CTAR_BR(brs.br) |
                      FREESCALE_DSPI_CTAR_PBR(brs.pbr);
                dspi_device->clocking.dspi_ctar = regval;

                return 0;

            } else {
                CYG_ASSERT (false, "Freescale DSPI:"
                            " Cannot run bus as slowly as requested.");
                return -1;
            }
        }
    default :
        break;
    }
    return -1;
}

// Update priority table and interrupt controller
void hal_interrupt_set_level(int vector, int level)
{
    cyg_uint32 index;
    
    CYG_ASSERT((0 <= (level) && 7 >= (level)), "Illegal level");
    CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)
                && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector");

    HAL_TRANSLATE_VECTOR(vector, index);
    cyg_hal_ILVL_table[index] = (cyg_uint8) level;

    hal_update_interrupt_controller(vector);
}

externC void cyg_drv_interrupt_set_cpu( cyg_vector_t vector, cyg_cpu_t cpu )
{
    CYG_REPORT_FUNCTION();
    CYG_REPORT_FUNCARG2("vector = %d, cpu = %d", vector, cpu);

    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");    
    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");

#ifdef CYGPKG_HAL_SMP_SUPPORT    
    HAL_INTERRUPT_SET_CPU( vector, cpu );
#endif
    
    CYG_REPORT_RETURN();
}