/***************************************************************************//**
 * @brief
 *   Configure the LESENSE alternate excitation modes.
 *
 * @details
 *   This function configures the alternate excitation channels of the LESENSE
 *   interface. Please refer to the configuration parameter type definition
 *   (LESENSE_ConfAltEx_TypeDef) for more details.
 *
 * @note
 *   Parameter @p useAltEx must be true in the channel configuration structrure
 *   (LESENSE_ChDesc_TypeDef) in order to use alternate excitation pins on the
 *   channel.
 *
 * @param[in] confAltEx
 *   Configuration structure for LESENSE alternate excitation pins.
 ******************************************************************************/
void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx)
{
  uint32_t i;
  uint32_t tmp;


  /* Configure alternate excitation mapping.
   * Atomic read-modify-write using BITBAND_Peripheral function in order to
   * support reconfiguration during LESENSE operation. */
  BITBAND_Peripheral(&(LESENSE->CTRL),
                     _LESENSE_CTRL_ALTEXMAP_SHIFT,
                     (uint32_t)confAltEx->altExMap);

  switch (confAltEx->altExMap)
  {
  case lesenseAltExMapALTEX:
    /* Iterate through the 8 possible alternate excitation pin descriptors. */
    for (i = 0U; i < 8U; ++i)
    {
      /* Enable/disable alternate excitation pin i.
       * Atomic read-modify-write using BITBAND_Peripheral function in order to
       * support reconfiguration during LESENSE operation. */
      BITBAND_Peripheral(&(LESENSE->ROUTE),
                         (16UL + i),
                         (uint32_t)confAltEx->AltEx[i].enablePin);
 
      /* Setup the idle phase state of alternate excitation pin i.
       * Read-modify-write in order to support reconfiguration during LESENSE
       * operation. */
      tmp                = (LESENSE->ALTEXCONF & ~((uint32_t)0x3UL << (i * 2UL)));
      tmp               |= ((uint32_t)confAltEx->AltEx[i].idleConf << (i * 2UL));
      LESENSE->ALTEXCONF = tmp;
      
      /* Enable/disable always excite on channel i */
      BITBAND_Peripheral(&(LESENSE->ALTEXCONF),
                         (16UL + i),
                         (uint32_t)confAltEx->AltEx[i].alwaysEx);
    }
    break;

  case lesenseAltExMapACMP:
    /* Iterate through all the 16 alternate excitation channels */
    for (i = 0U; i < 16U; ++i)
    {
      /* Enable/disable alternate ACMP excitation channel pin i. */
      /* Atomic read-modify-write using BITBAND_Peripheral function in order to
       * support reconfiguration during LESENSE operation. */
      BITBAND_Peripheral(&(LESENSE->ROUTE),
                         i,
                         (uint32_t)confAltEx->AltEx[i].enablePin);
    }
    break;
  default:
    /* Illegal value. */
    EFM_ASSERT(0);
  }
}

/***************************************************************************//**
 * @brief
 *   Restore BURTC to reset state
 * @note
 *   Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared.
 *   LOCK will not be reset to default value, as this will disable access
 *   to core BURTC registers.
 ******************************************************************************/
void BURTC_Reset(void)
{
  bool buResetState;

  /* Read reset state, set reset and restore state */
  buResetState = BITBAND_PeripheralRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT);
  BITBAND_Peripheral(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1);
  BITBAND_Peripheral(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);
}

__LINK_C error_t hw_gpio_enable_interrupt(pin_id_t pin_id)
{
    //to be absolutely safe we should put atomic blocks around this fuction but:
    //interrupts[..].interrupt_port && interrupts[..].callback will never change once they've
    //been properly set so I think we can risk it and avoid the overhead
    if(interrupts[pin_id.pin].interrupt_port != pin_id.port || interrupts[pin_id.pin].callback == 0x0)
    	return EOFF;

    BITBAND_Peripheral(&(GPIO->IFC), pin_id.pin, 1);
    BITBAND_Peripheral(&(GPIO->IEN), pin_id.pin, 1);
    return SUCCESS;
}

/***************************************************************************//**
 * @brief
 *   Configure write operation parameters for selected bank
 *
 * @param[in] banks
 *   Mask of memory bank(s) to configure write timing for
 *
 * @param[in] writeBufDisable
 *   If true, disable the write buffer
 *
 * @param[in] halfWE
 *   Enables or disables half cycle WE strobe in last strobe cycle
 ******************************************************************************/
void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
{
    /* Verify only valid banks are used */
    EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);

    /* Configure write operation parameters */
    if( banks & EBI_BANK0 )
    {
        BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
        BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
    }
    if( banks & EBI_BANK1 )
    {
        BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
        BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
    }
    if( banks & EBI_BANK2 )
    {
        BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
        BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
    }
    if( banks & EBI_BANK3 )
    {
        BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
        BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
    }
}

/***************************************************************************//**
 * @brief
 *   Initialize watchdog (assuming the watchdog configuration has not been
 *   locked).
 *
 * @note
 *   This function modifies the WDOG CTRL register which requires
 *   synchronization into the low frequency domain. If this register is modified
 *   before a previous update to the same register has completed, this function
 *   will stall until the previous synchronization has completed.
 *
 * @param[in] init
 *   Structure holding watchdog configuration. A default setting
 *   #WDOG_INIT_DEFAULT is available for init.
 ******************************************************************************/
void WDOG_Init(const WDOG_Init_TypeDef *init)
{
  uint32_t setting;

  if (init->enable)
  {
    setting = WDOG_CTRL_EN;
  }
  else
  {
    setting = 0;
  }

  if (init->debugRun)
  {
    setting |= WDOG_CTRL_DEBUGRUN;
  }

  if (init->em2Run)
  {
    setting |= WDOG_CTRL_EM2RUN;
  }

  if (init->em3Run)
  {
    setting |= WDOG_CTRL_EM3RUN;
  }

  if (init->em4Block)
  {
    setting |= WDOG_CTRL_EM4BLOCK;
  }

  if (init->swoscBlock)
  {
    setting |= WDOG_CTRL_SWOSCBLOCK;
  }

  setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) |
             ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);

  /* Wait for any pending previous write operation to have been completed in */
  /* low frequency domain */
  while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL) ;

  WDOG->CTRL = setting;

  /* Optional register locking */
  if (init->lock)
  {
    if (init->enable)
    {
      WDOG_Lock();
    }
    else
    {
      BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
    }
  }
}

/***************************************************************************//**
 * @brief
 *   Reset PCNT counter and TOP register.
 *
 * @param[in] pcnt
 *   Pointer to PCNT peripheral register block.
 ******************************************************************************/
void PCNT_CounterReset(PCNT_TypeDef *pcnt)
{
  EFM_ASSERT(PCNT_REF_VALID(pcnt));

  /* Notice that special SYNCBUSY handling is not applicable for the RSTEN */
  /* bit of the control register, so we don't need to wait for it when only */
  /* modifying RSTEN. (It would mean undefined wait time if clocked by */
  /* external clock.) The SYNCBUSY bit will however be set, leading to a */
  /* synchronization in the LF domain, with in reality no changes. */

  /* Enable reset of CNT and TOP register */
  BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);

  /* Disable reset of CNT and TOP register */
  BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
}

/***************************************************************************//**
 * @brief
 *
 *
 * @param[in] acmp
 *   Pointer to the ACMP peripheral register block.
 *
 * @param[in] init
 *   Pointer to initialization structure used to configure ACMP for capacative
 *   sensing operation.
 ******************************************************************************/
void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init)
{
  /* Make sure the module exists on the selected chip */
  EFM_ASSERT(ACMP_REF_VALID(acmp));

  /* Make sure biasprog is within bounds */
  EFM_ASSERT(init->biasProg < 16);

  /* Set control register. No need to set interrupt modes */
  acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT)
               | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT)
               | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT)
               | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT)
               | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT)
               | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT)
               | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT)
               | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT);

  acmp->INPUTSEL = (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
                   | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT);

  /* Enable ACMP if requested.
   * Note: BITBAND_Peripheral() function is used for setting/clearing single
   * bit peripheral register bitfields. */
  BITBAND_Peripheral(&(acmp->CTRL),
                     (uint32_t)_ACMP_CTRL_EN_SHIFT,
                     (uint32_t)init->enable);
}

/***************************************************************************//**
 * @brief
 *   Sets up the ACMP for use in capacative sense applications.
 *
 * @details
 *   This function sets up the ACMP for use in capacacitve sense applications.
 *   To use the capacative sense functionality in the ACMP you need to use
 *   the PRS output of the ACMP module to count the number of oscillations
 *   in the capacative sense circuit (possibly using a TIMER).
 *
 * @note
 *   A basic example of capacative sensing can be found in the STK BSP
 *   (capsense demo).
 *
 * @param[in] acmp
 *   Pointer to ACMP peripheral register block.
 *
 * @param[in] init
 *   Pointer to initialization structure used to configure ACMP for capacative
 *   sensing operation.
 ******************************************************************************/
void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init)
{
  /* Make sure the module exists on the selected chip */
  EFM_ASSERT(ACMP_REF_VALID(acmp));

  /* Make sure that vddLevel is within bounds */
  EFM_ASSERT(init->vddLevel < 64);

  /* Make sure biasprog is within bounds */
  EFM_ASSERT(init->biasProg < 16);

  /* Set control register. No need to set interrupt modes */
  acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT)
               | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT)
               | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT)
               | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT)
               | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT);

  /* Select capacative sensing mode by selecting a resistor and enabling it */
  acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT)
                   | ACMP_INPUTSEL_CSRESEN
                   | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
                   | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT)
                   | ACMP_INPUTSEL_NEGSEL_CAPSENSE;

  /* Enable ACMP if requested.
   * Note: BITBAND_Peripheral() function is used for setting/clearing single
   * bit peripheral register bitfields. */
  BITBAND_Peripheral(&(acmp->CTRL),
                     (uint32_t)_ACMP_CTRL_EN_SHIFT,
                     (uint32_t)init->enable);
}

/***************************************************************************//**
 * @brief
 *   Lock the watchdog configuration.
 *
 * @details
 *   This prevents errors from overwriting the watchdog configuration, possibly
 *   disabling it. Only a reset can unlock the watchdog config, once locked.
 *
 *   If the LFRCO or LFXO clocks are used to clock the watchdog, one should
 *   consider using the option of inhibiting those clocks to be disabled,
 *   please see the WDOG_Enable() init structure.
 *
 * @note
 *   This function modifies the WDOG CTRL register which requires
 *   synchronization into the low frequency domain. If this register is modified
 *   before a previous update to the same register has completed, this function
 *   will stall until the previous synchronization has completed.
 ******************************************************************************/
void WDOG_Lock(void)
{
  /* Wait for any pending previous write operation to have been completed in */
  /* low frequency domain */
  while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL) ;

  /* Disable writing to the control register */
  BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
}

/***************************************************************************//**
 * @brief
 *   Enable or disable EBI Bank
 *
 * @param[in] banks
 *   Banks to reconfigure, mask of EBI_BANK<n> flags
 *
 * @param[in] enable
 *   True to enable, false to disable
 ******************************************************************************/
void EBI_BankEnable(uint32_t banks, bool enable)
{
    if (banks & EBI_BANK0)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
    }
    if (banks & EBI_BANK1)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
    }
    if (banks & EBI_BANK2)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
    }
    if (banks & EBI_BANK3)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
    }
}

/***************************************************************************//**
 * @brief
 *   Enable/disable the watchdog timer.
 *
 * @note
 *   This function modifies the WDOG CTRL register which requires
 *   synchronization into the low frequency domain. If this register is modified
 *   before a previous update to the same register has completed, this function
 *   will stall until the previous synchronization has completed.
 *
 * @param[in] enable
 *   true to enable watchdog, false to disable. Watchdog cannot be disabled if
 *   watchdog has been locked.
 ******************************************************************************/
void WDOG_Enable(bool enable)
{
  if (!enable)
  {
    /* Wait for any pending previous write operation to have been completed in */
    /* low frequency domain */
    while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL) ;
  }
  BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_EN_SHIFT, (unsigned int) enable);
}

/***************************************************************************//**
 * @brief
 *   Enable or disable EBI Chip Select
 *
 * @param[in] cs
 *   ChipSelect lines to reconfigure, mask of EBI_CS<n> flags
 *
 * @param[in] enable
 *   True to enable, false to disable
 ******************************************************************************/
void EBI_ChipSelectEnable(uint32_t cs, bool enable)
{
    if (cs & EBI_CS0)
    {
        BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
    }
    if (cs & EBI_CS1)
    {
        BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
    }
    if (cs & EBI_CS2)
    {
        BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
    }
    if (cs & EBI_CS3)
    {
        BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
    }
}

/***************************************************************************//**
 * @brief
 *   Configure address operation parameters for selected bank
 *
 * @param[in] banks
 *   Mask of memory bank(s) to configure write timing for
 *
 * @param[in] halfALE
 *   Enables or disables half cycle ALE strobe in last strobe cycle
 ******************************************************************************/
void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
{
    /* Verify only valid banks are used */
    EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);

    if( banks & EBI_BANK0 )
    {
        BITBAND_Peripheral(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
    }
    if( banks & EBI_BANK1 )
    {
        BITBAND_Peripheral(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
    }
    if( banks & EBI_BANK2 )
    {
        BITBAND_Peripheral(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
    }
    if( banks & EBI_BANK3 )
    {
        BITBAND_Peripheral(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
    }
}

/***************************************************************************//**
 * @brief
 *   Clear the reset cause register.
 ******************************************************************************/
void RMU_ResetCauseClear(void)
{
    uint32_t locked;

    RMU->CMD = RMU_CMD_RCCLR;

    /* Clear some reset causes not cleared with RMU CMD register */
    /* (If EMU registers locked, they must be unlocked first) */
    locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
    if (locked)
    {
        EMU_Unlock();
    }

    BITBAND_Peripheral(&(EMU->AUXCTRL), 0, 1);
    BITBAND_Peripheral(&(EMU->AUXCTRL), 0, 0);

    if (locked)
    {
        EMU_Lock();
    }
}

/***************************************************************************//**
 * @brief
 *   Configure Backup Power Domain settings
 *
 * @param[in] bupdInit
 *   Backup power domain initialization structure
 ******************************************************************************/
void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
{
	uint32_t reg;

	/* Set power connection configuration */
	reg = EMU->PWRCONF & ~(
		_EMU_PWRCONF_PWRRES_MASK|
		_EMU_PWRCONF_VOUTSTRONG_MASK|
		_EMU_PWRCONF_VOUTMED_MASK|
		_EMU_PWRCONF_VOUTWEAK_MASK);

	reg |= (bupdInit->resistor|
		(bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)|
		(bupdInit->voutMed    << _EMU_PWRCONF_VOUTMED_SHIFT)|
		(bupdInit->voutWeak   << _EMU_PWRCONF_VOUTWEAK_SHIFT));

	EMU->PWRCONF = reg;

	/* Set backup domain inactive mode configuration */
	reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
	reg |= (bupdInit->inactivePower);
	EMU->BUINACT = reg;

	/* Set backup domain active mode configuration */
	reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK);
	reg |= (bupdInit->activePower);
	EMU->BUACT = reg;

	/* Set power control configuration */
	reg = EMU->BUCTRL & ~(
		_EMU_BUCTRL_PROBE_MASK|
		_EMU_BUCTRL_BODCAL_MASK|
		_EMU_BUCTRL_STATEN_MASK|
		_EMU_BUCTRL_EN_MASK);

	/* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
	   release reset */
	reg |= (bupdInit->probe|
		(bupdInit->bodCal          << _EMU_BUCTRL_BODCAL_SHIFT)|
		(bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)|
		(bupdInit->enable          << _EMU_BUCTRL_EN_SHIFT));

	/* Enable configuration */
	EMU->BUCTRL = reg;

	/* If enable is true, enable BU_VIN input power pin, if not disable it  */
	EMU_BUPinEnable(bupdInit->enable);

	/* If enable is true, release BU reset, if not keep reset asserted */
	BITBAND_Peripheral(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable);
}

/***************************************************************************//**
 * @brief
 *   Configure Byte Lane Enable for select banks
 *   timing support
 *
 * @param[in] banks
 *   Mask of memory bank(s) to configure polarity for
 *
 * @param[in] enable
 *   Flag
 ******************************************************************************/
void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
{
    /* Verify only valid banks are used */
    EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);

    /* Configure byte lane support for each selected bank */
    if (banks & EBI_BANK0)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
    }
    if (banks & EBI_BANK1)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
    }
    if (banks & EBI_BANK2)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
    }
    if (banks & EBI_BANK3)
    {
        BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
    }
}

/***************************************************************************//**
 * @brief
 *   Configure GPIO interrupt.
 *
 * @details
 *   If reconfiguring a GPIO interrupt that is already enabled, it is generally
 *   recommended to disable it first, see GPIO_Disable().
 *
 *   The actual GPIO interrupt handler must be in place before enabling the
 *   interrupt.
 *
 *   Notice that any pending interrupt for the selected pin is cleared by this
 *   function.
 *
 * @note
 *   A certain pin number can only be associated with one port. Ie, if GPIO
 *   interrupt 1 is assigned to port A/pin 1, then it is not possibly to use
 *   pin 1 from any other ports for interrupts. Please refer to the reference
 *   manual.
 *
 * @param[in] port
 *   The port to associate with @p pin.
 *
 * @param[in] pin
 *   The GPIO interrupt number (= port pin).
 *
 * @param[in] risingEdge
 *   Set to true if interrupts shall be enabled on rising edge, otherwise false.
 *
 * @param[in] fallingEdge
 *   Set to true if interrupts shall be enabled on falling edge, otherwise false.
 *
 * @param[in] enable
 *   Set to true if interrupt shall be enabled after configuration completed,
 *   false to leave disabled. See GPIO_IntDisable() and GPIO_IntEnable().
 ******************************************************************************/
void GPIO_IntConfig(GPIO_Port_TypeDef port,
                    unsigned int pin,
                    bool risingEdge,
                    bool fallingEdge,
                    bool enable)
{
  uint32_t tmp;

  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));

  /* There are two registers controlling the interrupt configuration:
   * The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls
   * pins 8-15. */
  if (pin < 8)
  {
    GPIO->EXTIPSELL = (GPIO->EXTIPSELL & ~(0xF << (4 * pin))) |
                      (port << (4 * pin));
  }
  else
  {
    tmp             = pin - 8;
    GPIO->EXTIPSELH = (GPIO->EXTIPSELH & ~(0xF << (4 * tmp))) |
                      (port << (4 * tmp));
  }

  /* Enable/disable rising edge */
  BITBAND_Peripheral(&(GPIO->EXTIRISE), pin, (unsigned int)risingEdge);

  /* Enable/disable falling edge */
  BITBAND_Peripheral(&(GPIO->EXTIFALL), pin, (unsigned int)fallingEdge);

  /* Clear any pending interrupt */
  GPIO->IFC = 1 << pin;

  /* Finally enable/disable interrupt */
  BITBAND_Peripheral(&(GPIO->IEN), pin, (unsigned int)enable);
}

/***************************************************************************//**
 * @brief
 *   Configure read operation parameters for selected bank
 *
 * @param[in] banks
 *   Mask of memory bank(s) to configure write timing for
 *
 * @param[in] pageMode
 *   Enables or disables half cycle WE strobe in last strobe cycle
 *
 * @param[in] prefetch
 *   Enables or disables half cycle WE strobe in last strobe cycle
 *
 * @param[in] halfRE
 *   Enables or disables half cycle WE strobe in last strobe cycle
 ******************************************************************************/
void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
{
    /* Verify only valid banks are used */
    EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);

    /* Configure read operation parameters */
    if( banks & EBI_BANK0 )
    {
        BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
        BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
        BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
    }
    if( banks & EBI_BANK1 )
    {
        BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
        BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
        BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
    }
    if( banks & EBI_BANK2 )
    {
        BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
        BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
        BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
    }
    if( banks & EBI_BANK3 )
    {
        BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
        BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
        BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
    }
}

//.........这里部分代码省略.........
              _EBI_CTRL_ARDYTODIS_MASK|
              _EBI_CTRL_BANK0EN_MASK|
              _EBI_CTRL_BANK1EN_MASK|
              _EBI_CTRL_BANK2EN_MASK|
              _EBI_CTRL_BANK3EN_MASK);
    if ( ebiInit->enable)
    {
        if ( ebiInit->banks & EBI_BANK0 )
        {
            ctrl |= EBI_CTRL_BANK0EN;
        }
        if ( ebiInit->banks & EBI_BANK1 )
        {
            ctrl |= EBI_CTRL_BANK1EN;
        }
        if ( ebiInit->banks & EBI_BANK2 )
        {
            ctrl |= EBI_CTRL_BANK2EN;
        }
        if ( ebiInit->banks & EBI_BANK3 )
        {
            ctrl |= EBI_CTRL_BANK3EN;
        }
    }
    ctrl |= ebiInit->mode;
    ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
    ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
#endif

    /* Configure timing */
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
    EBI_BankReadTimingSet(ebiInit->banks,
                          ebiInit->readSetupCycles,
                          ebiInit->readStrobeCycles,
                          ebiInit->readHoldCycles);
    EBI_BankReadTimingConfig(ebiInit->banks,
                             ebiInit->readPageMode,
                             ebiInit->readPrefetch,
                             ebiInit->readHalfRE);
    EBI_BankWriteTimingSet(ebiInit->banks,
                           ebiInit->writeSetupCycles,
                           ebiInit->writeStrobeCycles,
                           ebiInit->writeHoldCycles);
    EBI_BankWriteTimingConfig(ebiInit->banks,
                              ebiInit->writeBufferDisable,
                              ebiInit->writeHalfWE);
    EBI_BankAddressTimingSet(ebiInit->banks,
                             ebiInit->addrSetupCycles,
                             ebiInit->addrHoldCycles);
    EBI_BankAddressTimingConfig(ebiInit->banks,
                                ebiInit->addrHalfALE);
#else
    EBI_ReadTimingSet(ebiInit->readSetupCycles,
                      ebiInit->readStrobeCycles,
                      ebiInit->readHoldCycles);
    EBI_WriteTimingSet(ebiInit->writeSetupCycles,
                       ebiInit->writeStrobeCycles,
                       ebiInit->writeHoldCycles);
    EBI_AddressTimingSet(ebiInit->addrSetupCycles,
                         ebiInit->addrHoldCycles);
#endif

    /* Activate new configuration */
    EBI->CTRL = ctrl;

    /* Configure Adress Latch Enable */
    switch (ebiInit->mode)
    {
    case ebiModeD16A16ALE:
    case ebiModeD8A24ALE:
        /* Address Latch Enable */
        BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
        break;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
    case ebiModeD16:
#endif
    case ebiModeD8A8:
        /* Make sure Address Latch is disabled */
        BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
        break;
    }
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
    /* Limit pin enable */
    EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
    EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
    /* Location */
    EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;

    /* Enable EBI BL pin if necessary */
    if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
    {
        BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
    }
#endif
    /* Enable EBI pins EBI_WEn and EBI_REn */
    BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);

    /* Enable chip select lines */
    EBI_ChipSelectEnable(ebiInit->csLines, true);
}

/***************************************************************************//**
 * @brief
 *   Configure EBI pin polarity
 *
 * @param[in] line
 *   Which pin/line to configure
 *
 * @param[in] polarity
 *   Active high, or active low
 ******************************************************************************/
void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
{
    switch (line)
    {
    case ebiLineARDY:
        BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
        break;
    case ebiLineALE:
        BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
        break;
    case ebiLineWE:
        BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
        break;
    case ebiLineRE:
        BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
        break;
    case ebiLineCS:
        BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
        break;
#if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
    case ebiLineBL:
        BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
        break;
    case ebiLineTFTVSync:
        BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
        break;
    case ebiLineTFTHSync:
        BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
        break;
    case ebiLineTFTDataEn:
        BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
        break;
    case ebiLineTFTDClk:
        BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
        break;
    case ebiLineTFTCS:
        BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
        break;
#endif
    default:
        EFM_ASSERT(0);
        break;
    }
}