static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	if (val)
		ads->ds_ctl0 |= AR_ClrDestMask;
	else
		ads->ds_ctl0 &= ~AR_ClrDestMask;
}

static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
					u32 aggrLen)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
	ads->ds_ctl6 &= ~AR_AggrLen;
	ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
}

void
ar5416Set11nAggrLast(struct ath_hal *ah, void *ds)
{
    struct ar5416_desc *ads = AR5416DESC(ds);

    ads->ds_ctl1 |= AR_IsAggr;
    ads->ds_ctl1 &= ~AR_MoreAggr;
    ads->ds_ctl6 &= ~AR_PadDelim;
}

void
ar5416Set11nBurstDuration(struct ath_hal *ah, void *ds,
                                                  u_int burst_duration)
{
    struct ar5416_desc *ads = AR5416DESC(ds);

    ads->ds_ctl2 &= ~AR_BurstDur;
    ads->ds_ctl2 |= SM(burst_duration, AR_BurstDur);
}

void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
}

void
ar5416Set11nAggrFirst(struct ath_hal *ah, void *ds, u_int aggr_len)
{
    struct ar5416_desc *ads = AR5416DESC(ds);

    ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);

    ads->ds_ctl6 &= ~AR_AggrLen;
    ads->ds_ctl6 |= SM(aggr_len, AR_AggrLen);
}

void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
				    a_uint32_t vmf)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	if (vmf) {
		ads->ds_ctl0 |= AR_VirtMoreFrag;
	} else {
		ads->ds_ctl0 &= ~AR_VirtMoreFrag;
	}
}

void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
			      a_uint32_t numDelims)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);

	ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
	ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
		SM(numDelims, AR_PadDelim);
}

void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
				 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
				 a_uint32_t rtsctsDuration,
				 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
				 a_uint32_t flags)
{
        struct ar5416_desc *ads = AR5416DESC(ds);
        a_uint32_t ds_ctl0;

        HALASSERT(nseries == 4);
        (void)nseries;

        /*
         * Rate control settings override
         */
        if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
		ds_ctl0 = ads->ds_ctl0;

		if (flags & HAL_TXDESC_RTSENA) {
			ds_ctl0 &= ~AR_CTSEnable;
			ds_ctl0 |= AR_RTSEnable;
		} else {
			ds_ctl0 &= ~AR_RTSEnable;
			ds_ctl0 |= AR_CTSEnable;
		}

		ads->ds_ctl0 = ds_ctl0;
        }

        ads->ds_ctl2 = set11nTries(series, 0)
		|  set11nTries(series, 1)
		|  set11nTries(series, 2)
		|  set11nTries(series, 3)
		|  (durUpdateEn ? AR_DurUpdateEn : 0);

        ads->ds_ctl3 = set11nRate(series, 0)
		|  set11nRate(series, 1)
		|  set11nRate(series, 2)
		|  set11nRate(series, 3);

        ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
		|  set11nPktDurRTSCTS(series, 1);

        ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
		|  set11nPktDurRTSCTS(series, 3);

        ads->ds_ctl7 = set11nRateFlags(series, 0)
		|  set11nRateFlags(series, 1)
		|  set11nRateFlags(series, 2)
		|  set11nRateFlags(series, 3)
		| SM(rtsctsRate, AR_RTSCTSRate);
}

static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
					 u32 numDelims)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	unsigned int ctl6;

	ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);

	ctl6 = ads->ds_ctl6;
	ctl6 &= ~AR_PadDelim;
	ctl6 |= SM(numDelims, AR_PadDelim);
	ads->ds_ctl6 = ctl6;
}

void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
			  u32 size, u32 flags)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	struct ath9k_hw_capabilities *pCap = &ah->caps;

	ads->ds_ctl1 = size & AR_BufLen;
	if (flags & ATH9K_RXDESC_INTREQ)
		ads->ds_ctl1 |= AR_RxIntrReq;

	ads->ds_rxstatus8 &= ~AR_RxDone;
	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
		memset(&(ads->u), 0, sizeof(ads->u));
}

HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
			     a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
			     const struct ath_tx_desc *ds0)
{
        struct ar5416_desc *ads = AR5416DESC(ds);
        
//        a_uint32_t offset = 70;
//        char *data_ptr = ds->ds_data;
//        data_ptr[offset+0] = 'w';
//        data_ptr[offset+1] = 'e';
//        data_ptr[offset+2] = 'a';
//        data_ptr[offset+3] = 'r';
//        data_ptr[offset+4] = 'e';
//        data_ptr[offset+5] = 'h';
//        data_ptr[offset+6] = 'e';
//        data_ptr[offset+7] = 'r';
//        data_ptr[offset+8] = 'e';

        HALASSERT((segLen &~ AR_BufLen) == 0);

        if (firstSeg) {
                /*
                 * First descriptor, don't clobber xmit control data
                 * setup by ar5416SetupTxDesc.
                 */
                ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
        } else if (lastSeg) {
                /*
                 * Last descriptor in a multi-descriptor frame,
                 * copy the multi-rate transmit parameters from
                 * the first frame for processing on completion.
                 */
                ads->ds_ctl0 = 0;
                ads->ds_ctl1 = segLen;
                ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
                ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
        } else {
                /*
                 * Intermediate descriptor in a multi-descriptor frame.
                 */
                ads->ds_ctl0 = 0;
                ads->ds_ctl1 = segLen | AR_TxMore;
                ads->ds_ctl2 = 0;
                ads->ds_ctl3 = 0;
        }
        ads->ds_txstatus0 = ads->ds_txstatus1 = 0;

        return AH_TRUE;
}

void
ar5416Set11nTxDesc(struct ath_hal *ah, void *ds,
                                   u_int pktLen, HAL_PKT_TYPE type, u_int txPower,
                                   u_int key_ix, HAL_KEY_TYPE keyType,
                                   u_int flags)
{
        struct ar5416_desc *ads = AR5416DESC(ds);
		u_int32_t ctl0, ctl1, ctl6;
        HALASSERT(isValidPktType(type));
        HALASSERT(isValidKeyType(keyType));

        /*
         * If descriptor-based tpc, tx power is controlled by
         * ar5416Set11nRateScenario().
         * If not, what you put in the descriptor is ignored anyway.
         */
        txPower = 0;

        ctl0 = (pktLen & AR_FrameLen)
                                 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
                                 | SM(txPower, AR_XmitPower0)
                                 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
                                 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
                                 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
                                 | (key_ix != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
                                 | (flags & HAL_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);

        ctl1 = (key_ix != HAL_TXKEYIX_INVALID ? SM(key_ix, AR_DestIdx) : 0)
                                 | SM(type, AR_FrameType)
                                 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
                                 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
                                 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);

        ctl6 = SM(keyType, AR_EncrType);
		ads->ds_ctl0 = ctl0;
		ads->ds_ctl1 = ctl1;
		ads->ds_ctl6 = ctl6;

		/* For Kite set the tx antenna selection */
		if (AR_SREV_KITE(ah) || AR_SREV_K2(ah)) {
			/* FIXME: For now set the tx antenna to always 0,
			 * till tx selection diverisity is implementated
			 */
		    ads->ds_ctl8 = 0;
		    ads->ds_ctl9 = 0;
		    ads->ds_ctl10 = 0;
		    ads->ds_ctl11 = 0;
		}
}

void
ar5416Set11nVirtualMoreFrag(struct ath_hal *ah, void *ds,
                                                  u_int vmf)
{
    struct ar5416_desc *ads = AR5416DESC(ds);

    if (vmf)
    {
        ads->ds_ctl0 |=  AR_VirtMoreFrag;
    }
    else
    {
        ads->ds_ctl0 &= ~AR_VirtMoreFrag;
    }
}

void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	a_uint32_t ctl6;

	ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);

	/*
	 * We use a stack variable to manipulate ctl6 to reduce uncached 
	 * read modify, modfiy, write.
	 */
	ctl6 = ads->ds_ctl6;
	ctl6 &= ~AR_PadDelim;
	ctl6 |= SM(numDelims, AR_PadDelim);
	ads->ds_ctl6 = ctl6;
}

HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
			      a_uint32_t size, a_uint32_t flags)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	HALASSERT((size &~ AR_BufLen) == 0);

	ads->ds_ctl1 = size & AR_BufLen;
	if (flags & HAL_RXDESC_INTREQ)
		ads->ds_ctl1 |= AR_RxIntrReq;

	/* this should be enough */
	ads->ds_rxstatus8 &= ~AR_RxDone;

	return AH_TRUE;
}

/*
 * Process an RX descriptor, and return the status to the caller.
 * Copy some hardware specific items into a rx status object
 * provided by the caller.
 *
 * NB: the caller is responsible for validating the memory contents
 *     of the descriptor (e.g. flushing any cached copy).
 */
HAL_STATUS
ar5416ProcRxDescFast(struct ath_hal *ah, struct ath_desc *ds,
    u_int32_t pa, struct ath_desc *nds, struct ath_rx_status *rx_stats, void *buf_addr)
{
    struct ar5416_desc *ands = AR5416DESC(nds);

    /*
     * Given the use of a self-linked tail be very sure that the hw is
     * done with this descriptor; the hw may have done this descriptor
     * once and picked it up again...make sure the hw has moved on.
     */
    if ((ands->ds_rxstatus8 & AR_RxDone) == 0
        && OS_REG_READ(ah, AR_RXDP) == pa)
        return HAL_EINPROGRESS;

    return ar5416ProcRxDescBase(ah, ds, rx_stats);
}

HAL_BOOL
ar5416FillTxDesc(struct ath_hal *ah, void *ds, dma_addr_t *bufAddr,
        u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE keyType, HAL_BOOL first_seg,
        HAL_BOOL last_seg, const void *ds0)
{
        struct ar5416_desc *ads = AR5416DESC(ds);

        HALASSERT((seg_len[0] &~ AR_BufLen) == 0);
		OS_MEMZERO(&(ads->u.tx.tx_status), sizeof(ads->u.tx.tx_status));
        /* Set the buffer addresses */
        ads->ds_data = bufAddr[0];

        if (first_seg) {
                /*
                 * First descriptor, don't clobber xmit control data
                 * setup by ar5416SetupTxDesc.
                 */
                ads->ds_ctl1 |= seg_len[0] | (last_seg ? 0 : AR_TxMore);
        } else if (last_seg) {           /* !first_seg && last_seg */
                /*
                 * Last descriptor in a multi-descriptor frame,
                 * copy the multi-rate transmit parameters from
                 * the first frame for processing on completion.
                 */
                ads->ds_ctl0 = 0;
                ads->ds_ctl1 = seg_len[0];
#ifdef AH_NEED_DESC_SWAP
                ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
                ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
#else
                ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
                ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
#endif
        } else {                        /* !first_seg && !last_seg */
                /*
                 * Intermediate descriptor in a multi-descriptor frame.
                 */
                ads->ds_ctl0 = 0;
                ads->ds_ctl1 = seg_len[0] | AR_TxMore;
                ads->ds_ctl2 = 0;
                ads->ds_ctl3 = 0;
        }
        return AH_TRUE;
}

/*
 * Calculate air time of a transmit packet
 */
u_int32_t
ar5416CalcTxAirtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts,
        HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes)
{
    struct ar5416_desc *ads = AR5416DESC(ds);
    int finalindex_tries;
	int status9;
    /*
     * Number of attempts made on the final index
     * Note: If no BA was recv, then the data_fail_cnt is the number of tries
     * made on the final index.  If BA was recv, then add 1 to account for the
     * successful attempt.
     */
    finalindex_tries = ts->ts_longretry + (ts->ts_flags & HAL_TX_BA)? 1 : 0;

	/*
	 * Use a local copy of the ads in the cacheable memory to
	 * improve the d-cache efficiency.
	 */
	status9 = ads->ds_txstatus9;
	status9 = MS(status9, AR_FinalTxIdx);
    /*
     * Calculate time of transmit on air for packet including retries
     * at different rates.
     */
	if (status9 == 0) {
        return  MS(ads->ds_ctl4, AR_PacketDur0) * finalindex_tries;
	} else if (status9 == 1) {
        return (MS(ads->ds_ctl4, AR_PacketDur1) * finalindex_tries) +
               (MS(ads->ds_ctl2, AR_XmitDataTries0) * MS(ads->ds_ctl4, AR_PacketDur0));
	} else if (status9 == 2) {
        return (MS(ads->ds_ctl5, AR_PacketDur2) * finalindex_tries) +
               (MS(ads->ds_ctl2, AR_XmitDataTries1) * MS(ads->ds_ctl4, AR_PacketDur1)) +
               (MS(ads->ds_ctl2, AR_XmitDataTries0) * MS(ads->ds_ctl4, AR_PacketDur0));
	} else if (status9 == 3) {
        return (MS(ads->ds_ctl5, AR_PacketDur3) * finalindex_tries) +
               (MS(ads->ds_ctl2, AR_XmitDataTries2) * MS(ads->ds_ctl5, AR_PacketDur2)) +
               (MS(ads->ds_ctl2, AR_XmitDataTries1) * MS(ads->ds_ctl4, AR_PacketDur1)) +
               (MS(ads->ds_ctl2, AR_XmitDataTries0) * MS(ads->ds_ctl4, AR_PacketDur0));
	} else {
        HALASSERT(0);
        return 0;
    }
}

/*
 * Initialize RX descriptor, by clearing the status and setting
 * the size (and any other flags).
 */
HAL_BOOL
ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
    uint32_t size, u_int flags)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	HALASSERT((size &~ AR_BufLen) == 0);

	ads->ds_ctl1 = size & AR_BufLen;
	if (flags & HAL_RXDESC_INTREQ)
		ads->ds_ctl1 |= AR_RxIntrReq;

	/* this should be enough */
	ads->ds_rxstatus8 &= ~AR_RxDone;

	/* clear the rest of the status fields */
	OS_MEMZERO(&(ads->u), sizeof(ads->u));

	return AH_TRUE;
}