本文整理汇总了C++中llvm::MCInst类的典型用法代码示例。如果您正苦于以下问题:C++ MCInst类的具体用法?C++ MCInst怎么用?C++ MCInst使用的例子?那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了MCInst类的20个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于我们的系统推荐出更棒的C++代码示例。
示例1: printInst
static void printInst(const llvm::MCInst& inst) {
const llvm::MCInstrDesc& id = MII->get(inst.getOpcode());
llvm::outs() << MII->getName(inst.getOpcode()) << " (" << inst.getNumOperands() << ") ";
for (int iop = 0; iop < inst.getNumOperands(); ++iop) {
const llvm::MCOperand& op = inst.getOperand(iop);
if (op.isReg()) {
unsigned reg = op.getReg();
const char* rcName;
char clsn[128];
if (id.OpInfo[iop].RegClass < MRI->getNumRegClasses()) {
const llvm::MCRegisterClass& rc = MRI->getRegClass(id.OpInfo[iop].RegClass);
rcName = rc.getName();
} else {
snprintf(clsn, sizeof(clsn), "CLS%d", id.OpInfo[iop].RegClass);
rcName = clsn;
}
llvm::outs() << MRI->getName(reg) << "(" << rcName << ", " << (uint64_t)id.OpInfo[iop].OperandType << ")";
} else if (op.isImm()) {
llvm::outs() << op.getImm() << "(" << (uint64_t)id.OpInfo[iop].OperandType << ")";
} else {
llvm::outs() << "<UNK>";
}
llvm::outs() << ", ";
}
llvm::outs() << "\n";
}
开发者ID:OSLL,项目名称:llvm,代码行数:31,代码来源:llvm-analyze.cpp
示例2: SignedBits
bool
EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn)
{
bool success = false;
const uint32_t imm16 = insn.getOperand(2).getImm();
uint32_t imm = SignedBits(imm16, 15, 0);
uint64_t result;
uint32_t src, dst;
dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
/* Check if this is addiu sp,<src>,imm16 */
if (dst == gcc_dwarf_sp_mips64)
{
/* read <src> register */
uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, 0, &success);
if (!success)
return false;
result = src_opd_val + imm;
Context context;
RegisterInfo reg_info_sp;
if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips64, reg_info_sp))
context.SetRegisterPlusOffset (reg_info_sp, imm);
/* We are allocating bytes on stack */
context.type = eContextAdjustStackPointer;
WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips64, result);
}
return true;
}
开发者ID:newappfirst,项目名称:lldb,代码行数:35,代码来源:EmulateInstructionMIPS.cpp
示例3:
bool
EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn)
{
uint32_t src, base;
src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src))
{
RegisterValue data_src;
RegisterInfo reg_info_src;
if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src))
return false;
Context context;
context.type = eContextRegisterLoad;
if (!WriteRegister (context, ®_info_src, data_src))
return false;
return true;
}
return false;
}
开发者ID:newappfirst,项目名称:lldb,代码行数:27,代码来源:EmulateInstructionMIPS.cpp
示例4: getLocalName
static std::string getLocalName(const llvm::MCInst& inst, unsigned iop) {
const llvm::MCOperand& op = inst.getOperand(iop);
if (op.isReg() && strcmp(MRI->getName(op.getReg()), "RBP") == 0) {
char buf[128];
snprintf(buf, 128, "local_%x", -inst.getOperand(iop + 3).getImm());
return std::string(buf);
} else {
return std::string("UNK");
}
}
开发者ID:OSLL,项目名称:llvm,代码行数:12,代码来源:llvm-analyze.cpp
示例5: DecodeSingleIndexedInstruction
static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Rt = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
unsigned Opc = fieldFromInstruction(Insn, 22, 2);
unsigned V = fieldFromInstruction(Insn, 26, 1);
unsigned Size = fieldFromInstruction(Insn, 30, 2);
if (Opc == 0 || (V == 1 && Opc == 2)) {
// It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
}
if (V == 0 && (Opc == 2 || Size == 3)) {
DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
} else if (V == 0) {
DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
} else if (V == 1 && (Opc & 2)) {
DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
} else {
switch (Size) {
case 0:
DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
break;
case 1:
DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
break;
case 2:
DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
break;
case 3:
DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
break;
}
}
if (Opc != 0 && (V != 1 || Opc != 2)) {
// It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
}
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Imm9));
// N.b. The official documentation says undpredictable if Rt == Rn, but this
// takes place at the architectural rather than encoding level:
//
// "STR xzr, [sp], #4" is perfectly valid.
if (V == 0 && Rt == Rn && Rn != 31)
return MCDisassembler::SoftFail;
else
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:58,代码来源:AArch64Disassembler.cpp
示例6: DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Register));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:9,代码来源:AArch64Disassembler.cpp
示例7: DecodeFPZeroOperand
static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
unsigned RmBits,
uint64_t Address,
const void *Decoder) {
// Any bits are valid in the instruction (they're architecturally ignored),
// but a code generator should insert 0.
Inst.addOperand(MCOperand::CreateImm(0));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:9,代码来源:AArch64Disassembler.cpp
示例8:
DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
unsigned Imm,
uint64_t Addr) const {
unsigned RegID;
if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
Inst.addOperand(MCOperand::createReg(RegID));
return MCDisassembler::Success;
}
return MCDisassembler::Fail;
}
开发者ID:UBERLLVM,项目名称:llvm,代码行数:10,代码来源:AMDGPUDisassembler.cpp
示例9: DecodeRegisterClassByID
static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo,
unsigned RegID,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
uint16_t Register = getReg(Decoder, RegID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Register));
return MCDisassembler::Success;
}
开发者ID:EasyHard,项目名称:vurd,代码行数:10,代码来源:AArch64Disassembler.cpp
示例10: DecodeRegExtendOperand
static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
unsigned ShiftAmount,
uint64_t Address,
const void *Decoder) {
// Only values 0-4 are valid for this 3-bit field
if (ShiftAmount > 4)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:11,代码来源:AArch64Disassembler.cpp
示例11: DecodeLogicalImmOperand
static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
unsigned Bits,
uint64_t Address,
const void *Decoder) {
uint64_t Imm;
if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Bits));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:11,代码来源:AArch64Disassembler.cpp
示例12: DecodeCVT32FixedPosOperand
static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
unsigned Imm6Bits,
uint64_t Address,
const void *Decoder) {
// 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
if (Imm6Bits < 32)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:11,代码来源:AArch64Disassembler.cpp
示例13: Decode32BitShiftOperand
static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
unsigned ShiftAmount,
uint64_t Address,
const void *Decoder) {
// Only values below 32 are valid for a 32-bit register
if (ShiftAmount > 31)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:11,代码来源:AArch64Disassembler.cpp
示例14: DecodeSysRegOperand
static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
llvm::MCInst &Inst,
unsigned Val,
uint64_t Address,
const void *Decoder) {
bool ValidNamed;
Mapper.toString(Val, ValidNamed);
Inst.addOperand(MCOperand::CreateImm(Val));
return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:12,代码来源:AArch64Disassembler.cpp
示例15: DecodeBitfield32ImmOperand
static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
unsigned Imm6Bits,
uint64_t Address,
const void *Decoder) {
// In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
// between 0 and 31.
if (Imm6Bits > 31)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:12,代码来源:AArch64Disassembler.cpp
示例16: DecodeAddrRegExtendOperand
static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
unsigned OptionHiS,
uint64_t Address,
const void *Decoder) {
// Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
// S}. Hence we want to check bit 1.
if (!(OptionHiS & 2))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(OptionHiS));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:12,代码来源:AArch64Disassembler.cpp
示例17: DecodeMoveWideImmOperand
static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
unsigned FullImm,
uint64_t Address,
const void *Decoder) {
unsigned Imm16 = FullImm & 0xffff;
unsigned Shift = FullImm >> 16;
if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Imm16));
Inst.addOperand(MCOperand::CreateImm(Shift));
return MCDisassembler::Success;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:13,代码来源:AArch64Disassembler.cpp
示例18: DecodeNamedImmOperand
static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
unsigned Val,
uint64_t Address,
const void *Decoder) {
SomeNamedImmMapper Mapper;
bool ValidNamed;
Mapper.toString(Val, ValidNamed);
if (ValidNamed || Mapper.validImm(Val)) {
Inst.addOperand(MCOperand::CreateImm(Val));
return MCDisassembler::Success;
}
return MCDisassembler::Fail;
}
开发者ID:8l,项目名称:emscripten-fastcomp,代码行数:14,代码来源:AArch64Disassembler.cpp
示例19: ArchDecodeInstruction
// Decodes the instruction, and returns the number of bytes decoded.
size_t ArchDecodeInstruction(const uint8_t *bytes, const uint8_t *bytes_end,
uintptr_t va, llvm::MCInst &inst) {
size_t total_size = 0;
size_t max_size = static_cast<size_t>(bytes_end - bytes);
std::unordered_set<unsigned> prefixes;
for (; total_size < max_size; ) {
llvm::ArrayRef<uint8_t> bytes_to_decode(
&(bytes[total_size]), max_size - total_size);
uint64_t size = 0;
auto decode_status = gDisassembler->getInstruction(
inst, size, bytes_to_decode, va, llvm::nulls(), llvm::nulls());
if (llvm::MCDisassembler::Success != decode_status) {
return 0;
}
total_size += size;
switch (auto op_code = inst.getOpcode()) {
case llvm::X86::CS_PREFIX:
case llvm::X86::DATA16_PREFIX:
case llvm::X86::DS_PREFIX:
case llvm::X86::ES_PREFIX:
case llvm::X86::FS_PREFIX:
case llvm::X86::GS_PREFIX:
case llvm::X86::LOCK_PREFIX:
case llvm::X86::REPNE_PREFIX:
case llvm::X86::REP_PREFIX:
case llvm::X86::REX64_PREFIX:
case llvm::X86::SS_PREFIX:
case llvm::X86::XACQUIRE_PREFIX:
case llvm::X86::XRELEASE_PREFIX:
prefixes.insert(op_code);
break;
default:
max_size = 0; // Stop decoding.
break;
}
}
FixupInstruction(inst, prefixes);
return total_size;
}
开发者ID:kumarak,项目名称:mcsema,代码行数:50,代码来源:Arch.cpp
示例20: DecodeNeonMovImmShiftOperand
static DecodeStatus
DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
uint64_t Address, const void *Decoder) {
bool IsLSL = false;
if (Ext == A64SE::LSL)
IsLSL = true;
else if (Ext != A64SE::MSL)
return MCDisassembler::Fail;
// MSL and LSLH accepts encoded shift amount 0 or 1.
if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
return MCDisassembler::Fail;
// LSL accepts encoded shift amount 0, 1, 2 or 3.
if (IsLSL && ShiftAmount > 3)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
return MCDisassembler::Success;
}
开发者ID:EasyHard,项目名称:vurd,代码行数:20,代码来源:AArch64Disassembler.cpp
注:本文中的llvm::MCInst类示例由纯净天空整理自Github/MSDocs等源码及文档管理平台,相关代码片段筛选自各路编程大神贡献的开源项目,源码版权归原作者所有,传播和使用请参考对应项目的License;未经允许,请勿转载。 |
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