what this error mean for Yosys synthesis tool

Question

I am trying to synthesise a verilog design using yosys however I get following error that is not very helpful. I am not even sure which part of the code the tool is complaining about. (Just to add I have simulated the design with Modelsim and no problem with that)

I would appreciate it if someone could help me with this.

Warning: Replacing memory cnt_CHKN_proc with list of registers. See RTL/Decode.sv:410
ERROR: Assert `arg->is_signed == sig.as_wire()->is_signed' failed in frontends/ast/genrtlil.cc:1738.

question from:https://stackoverflow.com/questions/66066392/what-this-error-mean-for-yosys-synthesis-tool

Answer 1

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