vhdl - An issue regarding multiple drivers on a wire, error: [DRC MDRV-1] Multiple Driver Nets: Net led_OBUF[0] has multiple drivers: led_OBUF[0]_inst_i_1/O

Question

I am creating a simple VHDL code which should create two 4 bit binary numbers (A and B) using 8 inputs (4 for each), then based on one of three buttons being pressed, a logic function is performed on A and B, either AND, OR, or XOR.

My concern is that I am trying to map multiple input signals to a single port, and multiple output signals to a single port, however my confusion lies in the fact that I have successfully implemented a very similar description without any errors, I will show the non error description at the end. If my suspicions are correct, please could someone explain to me why the error does not occur on the bottom code?

Code with errors:

use IEEE.STD_LOGIC_1164.ALL;

entity Lab_2_Source_File is
port(A : in STD_LOGIC_VECTOR(3 downto 0);
     B : in STD_LOGIC_VECTOR(3 downto 0);
     btnd : in STD_LOGIC;
     btnl : in STD_LOGIC;
     btnr : in STD_LOGIC;
     led : out STD_LOGIC_VECTOR(3 downto 0)
     );
end Lab_2_Source_File;


architecture Behavioral of Lab_2_Source_File is
begin 

process(btnd)
begin
led(0) <=A(0) and B(0);
led(1) <=A(1) and B(1);
led(2) <=A(2) and B(2);
led(3) <=A(3) and B(3);
end process;

process(btnl)
begin
led(0) <=A(0) or B(0);
led(1) <=A(1) or B(1);
led(2) <=A(2) or B(2);
led(3) <=A(3) or B(3);
end process;

process(btnr)
begin
led(0) <=A(0) xor B(0);
led(1) <=A(1) xor B(1);
led(2) <=A(2) xor B(2);
led(3) <=A(3) xor B(3);
end process;

end Behavioral;

I modified the constraints file accordingly

set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { led }]; #IO_L15P_T2_DQS_13 Sch=led[0]

## Switches

set_property -dict { PACKAGE_PIN E22  IOSTANDARD LVCMOS12 } [get_ports { A }]; #IO_L22P_T3_16 Sch=sw[0]

set_property -dict { PACKAGE_PIN F21  IOSTANDARD LVCMOS12 } [get_ports { B }]; #IO_25_16 Sch=sw[1]

Here is the error

[DRC MDRV-1] Multiple Driver Nets: Net led_OBUF[0] has multiple drivers:led_OBUF[0]_inst_i_1/O, led_OBUF[0]_inst_i_3/O, and led_OBUF[0]_inst_i_2/O.

The second code, with no errors. I show this code because I am unsure of how 4 inputs (3 downto 0) can be mapped to a single input. I have named the ports using the original port names in the constraint file.

port(sw0 : in STD_LOGIC_VECTOR(3 downto 0);
led0: out STD_LOGIC_VECTOR(3 downto 0)
);

end Lab_2_Source_File;

architecture Behavioral of Lab_2_Source_File is
begin 

process(sw0) 
begin 

led0<=sw0;

end process; 
end Behavioral;

As mentioned above, the error leads me to beleive that it is due to trying to map multiple signals to the led output, however whilst this makes sense, I am confused as the same error does not occur when I map multiple signals to the output on the other code. Please could someone help me explain what's going on?

Answer 1

the error leads me to beleive that it is due to trying to map multiple signals to the led output

This is correct.

however whilst this makes sense, I am confused as the same error does not occur when I map multiple signals to the output on the other code.

In the last example,

led0<=sw0;

the only driver for led0(0) is sw0(0), and the only driver for led0(1) is sw0(1), and so on. So there are no multiple drivers for one net, as in the first example, which is why there is no error.